Searched hist:12 (Results 1276 - 1300 of 2449) sorted by relevance
/gem5/tests/long/se/30.eon/ref/arm/linux/o3-timing/ | ||
H A D | config.ini | 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 9370:5172ffaf6e30 Wed Dec 12 10:51:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> arm regressions: updates to config.ini, terminal files 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/ | ||
H A D | config.ini | 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 9370:5172ffaf6e30 Wed Dec 12 10:51:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> arm regressions: updates to config.ini, terminal files 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/ | ||
H A D | config.ini | 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 9370:5172ffaf6e30 Wed Dec 12 10:51:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> arm regressions: updates to config.ini, terminal files 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/ | ||
H A D | config.ini | 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 9370:5172ffaf6e30 Wed Dec 12 10:51:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> arm regressions: updates to config.ini, terminal files 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ | ||
H A D | stats.txt | 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming 9698:db85c5348a96 Tue May 21 12:32:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> stats: updates statistics for ruby regressions 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/ | ||
H A D | stats.txt | 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming 9698:db85c5348a96 Tue May 21 12:32:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> stats: updates statistics for ruby regressions 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/ | ||
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 10535:4ccec5baf82c Wed Nov 12 09:05:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump regressions to match latest changes Updates after timezone hick-up and sorting of dictionary items in the SimObject. 10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/long/se/10.mcf/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/ | ||
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9702:094d0280e481 Tue May 21 12:41:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> x86, regressions: updates stats This is due to op class, function call, walker patches. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9013:afa278317136 Tue May 22 12:38:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86 Regression: update stats due to cc register split 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/long/se/70.twolf/ref/arm/linux/o3-timing/ | ||
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/ | ||
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9702:094d0280e481 Tue May 21 12:41:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> x86, regressions: updates stats This is due to op class, function call, walker patches. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9013:afa278317136 Tue May 22 12:38:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86 Regression: update stats due to cc register split 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/ | ||
H A D | stats.txt | 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes 11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references 11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references Change-Id: Ic827213134b199446822f128b81d4a480e777fee 11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes This patch updates the stats to reflect the changes to the DRAM controller. 9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes 9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes. |
/gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/ | ||
H A D | stats.txt | 11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes 10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming 9702:094d0280e481 Tue May 21 12:41:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> x86, regressions: updates stats This is due to op class, function call, walker patches. 9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles This patch updates the stats to reflect the change in how cache latencies are expressed. In addition, the latencies are now rounded to multiples of the clock period, thus also affecting other stats. 9013:afa278317136 Tue May 22 12:38:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86 Regression: update stats due to cc register split 8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes |
/gem5/src/arch/x86/isa/microops/ | ||
H A D | limmop.isa | 7626:bdd926760470 Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of the flagless microop constructor. This will reduce clutter in the source and hopefully speed up compilation. 7620:3d8a23caa1ef Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Consolidate extra microop flags into one parameter. This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor. 6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands. 4693:ca44a1014212 Tue Jul 17 21:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make disassembled x86 register indices reflect their size. This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly. 4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent. src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. 4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent. src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. |
H A D | specop.isa | 9010:7891b96e1526 Tue May 22 12:29:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86: Split Condition Code register This patch moves the ECF and EZF bits to individual registers (ecfBit and ezfBit) and the CF and OF bits to cfofFlag registers. This is being done so as to lower the read after write dependencies on the the condition code register. Ultimately we will have the following registers [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Note that this is only one part of the solution for lowering the dependencies. The other part will check whether or not the condition code register needs to be actually read. This would be done through a separate patch. 7626:bdd926760470 Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of the flagless microop constructor. This will reduce clutter in the source and hopefully speed up compilation. 7620:3d8a23caa1ef Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Consolidate extra microop flags into one parameter. This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor. 5449:89b696c8b754 Thu Jun 12 00:58:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the disassembly for halt conform with the other microops. 4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent. src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. 4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent. src/arch/x86/isa/macroop.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code. src/arch/x86/isa/microops/base.isa: Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation. |
H A D | regop.isa | 9699:76828cbe5de4 Tue May 21 12:33:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> x86: add op class for int and fp microops in isa description Currently all the integer microops are marked as IntAluOp and the floating point microops are marked as FloatAddOp. This patch adds support for marking different microops differently. Now IntMultOp, IntDivOp, FloatDivOp, FloatMultOp, FloatCvtOp, FloatSqrtOp classes will be used as well. This will help in providing different latencies for different op class. 9010:7891b96e1526 Tue May 22 12:29:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86: Split Condition Code register This patch moves the ECF and EZF bits to individual registers (ecfBit and ezfBit) and the CF and OF bits to cfofFlag registers. This is being done so as to lower the read after write dependencies on the the condition code register. Ultimately we will have the following registers [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Note that this is only one part of the solution for lowering the dependencies. The other part will check whether or not the condition code register needs to be actually read. This would be done through a separate patch. 7626:bdd926760470 Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of the flagless microop constructor. This will reduce clutter in the source and hopefully speed up compilation. 7620:3d8a23caa1ef Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Consolidate extra microop flags into one parameter. This single parameter replaces the collection of bools that set up various flavors of microops. A flag parameter also allows other flags to be set like the serialize before/after flags, etc., without having to change the constructor. 7080:c52c581277bf Wed May 12 03:49:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Actual change that fixes div. How did that happen? 6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands. 5675:7828ee363019 Sun Oct 12 23:38:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement the chks check of interrupt gate target code segments. 5674:4a4f20dfbc60 Sun Oct 12 23:33:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add a check type for interrupt gates. 5673:57be483cea36 Sun Oct 12 23:29:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Fix chks checking the submode for stack segments. 5672:f332946e12b2 Sun Oct 12 23:25:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Let segment manipulation microops be conditional. |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | mem.isa | 13587:9d4da35335af Fri Jan 18 12:14:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Remove SWP and SWPB instructions The SWP and SWPB instructions have been removed from AArch32. It was previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits, which are now hardcoded to 0b0000 (SWP and SWPB not implemented) Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15815 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 12788:fe6d6ae79d7c Thu Jun 07 12:17:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: BadMode checking if corresponding EL is implemented The old utility function called badMode was only checking if the mode passed as an argument was a recognized mode. It was not checking if the corresponding mode/EL was implemented. That function has been renamed to unknownMode and a new badMode has been introduced. This is used by the cpsrWriteByInstruction function. In this way any try to change the execution mode won't succeed if the mode hasn't been implemented. Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11196 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 6245:f8692407cc23 Sun Jun 21 12:41:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of unnecessary fp_enable_checks. 6243:3a1698fbbc9f Sun Jun 21 12:37:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make the isa parser aware that CPSR is being used. 6242:1cee707c1228 Sun Jun 21 12:21:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Pull some static code out of the isa desc and create miscregs.hh. 6241:29c1cc8075e4 Sun Jun 21 12:16:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Get rid of unused postacc_code. |
H A D | macromem.isa | 7130:12d7f945261f Wed Jun 02 01:58:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> ARM: Eliminate decoding for the very deprecated FPA instructions. 6243:3a1698fbbc9f Sun Jun 21 12:37:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> ARM: Make the isa parser aware that CPSR is being used. |
/gem5/src/arch/x86/ | ||
H A D | tlb.cc | 9294:8fb03b13de02 Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Port: Add protocol-agnostic ports in the port hierarchy This patch adds an additional level of ports in the inheritance hierarchy, separating out the protocol-specific and protocl-agnostic parts. All the functionality related to the binding of ports is now confined to use BaseMaster/BaseSlavePorts, and all the protocol-specific parts stay in the Master/SlavePort. In the future it will be possible to add other protocol-specific implementations. The functions used in the binding of ports, i.e. getMaster/SlavePort now use the base classes, and the index parameter is updated to use the PortID typedef with the symbolic InvalidPortID as the default. 8953:488d45aeb672 Sun Apr 15 02:24:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Use the AddrTrie class to implement the TLB. This change also adjusts the TlbEntry class so that it stores the number of address bits wide a page is rather than its size in bytes. In other words, instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K, but it's a little harder going the other way. 8953:488d45aeb672 Sun Apr 15 02:24:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Use the AddrTrie class to implement the TLB. This change also adjusts the TlbEntry class so that it stores the number of address bits wide a page is rather than its size in bytes. In other words, instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K, but it's a little harder going the other way. 8864:fe907afe14a3 Thu Mar 01 12:37:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> x86: Fix x86 TLB and Walker This patch adds a function to X86 tlb that returns the walker port. This port is required for correctly connecting the walker ports for the cpu just switched in 8646:ef6cbf0f14dc Thu Jan 05 12:00:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> X86 TLB: Move a DPRINTF to its correct place The DPRINTF for doing protection checks appears after the checks have been carried out. It is possible that the function returns while the checks are being carried, in which case the printf is missed out. This patch moves the DPRINTF before the checks. 7625:b1e69203bae9 Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Make the TLB fault instead of panic when something is unmapped in SE mode. The fault object, if invoked, would then panic. This is a bit less direct, but it means speculative execution won't panic the simulator. 5965:71f8d7c12619 Fri Feb 27 12:23:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix segment limit checks. 5648:e8abda6e0980 Sun Oct 12 14:08:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the local APIC accessible through the memory system directly, and make the timer work. 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. 5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object. |
/gem5/src/mem/slicc/ast/ | ||
H A D | IfStatementAST.py | 9628:195d92059654 Tue Apr 09 17:12:00 EDT 2013 Jason Power <powerjg@cs.wisc.edu> Ruby: Fix typo in Slicc if-statement AST error The error in the SLICC code was hidden by the python error in SLICC parser before this patch 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
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