Searched hist:10041 (Results 1 - 4 of 4) sorted by relevance
| /gem5/configs/common/ | ||
| H A D | MemConfig.py | 10041:fae4550d2103 Mon Jan 27 19:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> config: allow more than 3GB of memory for x86 simulations This patch edits the configuration files so that x86 simulations can have more than 3GB of memory. It also corrects a bug in the MemConfig.py script. |
| H A D | FSConfig.py | 10041:fae4550d2103 Mon Jan 27 19:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> config: allow more than 3GB of memory for x86 simulations This patch edits the configuration files so that x86 simulations can have more than 3GB of memory. It also corrects a bug in the MemConfig.py script. |
| /gem5/configs/example/ | ||
| H A D | fs.py | 10041:fae4550d2103 Mon Jan 27 19:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> config: allow more than 3GB of memory for x86 simulations This patch edits the configuration files so that x86 simulations can have more than 3GB of memory. It also corrects a bug in the MemConfig.py script. |
| /gem5/src/arch/arm/ | ||
| H A D | isa.cc | 12666:bea22b5e6cf7 Mon Dec 11 08:20:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Using explicit invalidation in TLB When setting TLB related MiscRegs, using explicit TLB regs invalidation rather than implicit switch-case fallthrough Change-Id: Ia1a7358b6d54dda3811be1c5ce5d676f8c518c4d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10041 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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