| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | exit_gen.hh | 59 ExitGen(SimObject &obj, MasterID master_id, Tick _duration) argument
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| H A D | idle_gen.hh | 64 IdleGen(SimObject &obj, MasterID master_id, Tick _duration) argument
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| H A D | linear_gen.hh | 86 LinearGen(SimObject &obj, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit) argument
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| H A D | random_gen.hh | 82 RandomGen(SimObject &obj, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit) argument
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| H A D | dram_gen.cc | 52 DramGen(SimObject &obj, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit, unsigned int num_seq_pkts, unsigned int page_size, unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util, unsigned int addr_mapping, unsigned int nbr_of_ranks) argument
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| H A D | base_gen.cc | 54 BaseGen::BaseGen(SimObject &obj, MasterID master_id, Tick _duration) argument
83 StochasticGen(SimObject &obj, MasterID master_id, Tick _duration, Addr start_addr, Addr end_addr, Addr _blocksize, Addr cacheline_size, Tick min_period, Tick max_period, uint8_t read_percent, Addr data_limit) argument
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| H A D | dram_rot_gen.hh | 90 DramRotGen(SimObject &obj, MasterID master_id, Tick _duration, argument
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| H A D | trace_gen.hh | 161 TraceGen(SimObject &obj, MasterID master_id, Tick _duration, argument
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| /gem5/src/mem/ |
| H A D | mem_master.hh | 56 MasterInfo(const SimObject* _obj, std::string master_name, MasterID master_id) argument
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| /gem5/src/mem/cache/tags/ |
| H A D | base.cc | 109 MasterID master_id = pkt->req->masterId(); local
114 blk->insert(extractTag(pkt->getAddr()), pkt->isSecure(), master_id, local
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| /gem5/src/mem/cache/prefetch/ |
| H A D | stride.cc | 153 MasterID master_id = useMasterId ? pfi.getMasterId() : 0; local
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| /gem5/src/arch/arm/ |
| H A D | tlb.cc | 111 TLB::setMMU(Stage2MMU *m, MasterID master_id) argument
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| H A D | table_walker.cc | 102 TableWalker::setMMU(Stage2MMU *m, MasterID master_id) argument
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| /gem5/src/cpu/trace/ |
| H A D | trace_cpu.hh | 429 FixedRetryGen(TraceCPU& _owner, const std::string& _name, MasterPort& _port, MasterID master_id, const std::string& trace_file) argument
856 ElasticDataGen(TraceCPU& _owner, const std::string& _name, MasterPort& _port, MasterID master_id, const std::string& trace_file, TraceCPUParams *params) argument
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