| /gem5/ext/mcpat/ |
| H A D | core.cc | 61 int idx, tag, data, size, line, assoc, banks; local
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| /gem5/src/arch/hsail/ |
| H A D | operand.hh | 757 getSrcOperand(int idx) argument
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| /gem5/src/base/ |
| H A D | circular_queue.hh | 159 iterator(CircularQueue* cq, uint32_t idx, uint32_t round) argument
407 size_t idx() const { return _idx; } function in struct:CircularQueue::iterator
457 isValidIdx(size_t idx, uint32_t round) const argument
639 getIterator(size_t idx) argument
[all...] |
| /gem5/src/dev/net/ |
| H A D | ns_gige.cc | 177 NSGigE::getPort(const std::string &if_name, PortID idx) argument
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| H A D | sinic.cc | 146 Device::getPort(const std::string &if_name, PortID idx) argument
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| H A D | i8254xGBe.cc | 143 IGbE::getPort(const std::string &if_name, PortID idx) argument
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| /gem5/src/dev/virtio/ |
| H A D | base.hh | 764 void setQueueSelect(QueueID idx) { _queueSelect = idx; } argument
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| /gem5/src/sim/ |
| H A D | pseudo_inst.cc | 344 string::size_type idx = buffer.find(' '); local
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| /gem5/src/cpu/pred/ |
| H A D | statistical_corrector.hh | 97 unsigned idx = ordinal - 1; local
105 unsigned idx = ordinal - 1; local
122 unsigned getEntry(Addr pc, unsigned idx) argument
[all...] |
| H A D | multiperspective_perceptron_tage.cc | 453 unsigned int idx = getIndex(tid, bi, *specs[i], i); local
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| /gem5/src/cpu/checker/ |
| H A D | cpu.hh | 270 setVecLaneOperandT(const StaticInst *si, int idx, const LD& val) argument
[all...] |
| /gem5/src/arch/arm/insts/ |
| H A D | vfp.cc | 1157 VfpMacroOp::addStride(IntRegIndex idx, unsigned stride) argument
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| /gem5/src/mem/cache/ |
| H A D | base.cc | 190 BaseCache::getPort(const std::string &if_name, PortID idx) argument
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| /gem5/src/cpu/kvm/ |
| H A D | x86_cpu.cc | 381 checkSeg(const char *name, const int idx, const struct kvm_segment &seg, argument
[all...] |
| /gem5/src/systemc/core/ |
| H A D | sc_module.cc | 119 sc_module::gem5_getPort(const std::string &if_name, int idx) argument
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| /gem5/src/gpu-compute/ |
| H A D | gpu_tlb.cc | 135 GpuTLB::getPort(const std::string &if_name, PortID idx) argument
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| /gem5/src/cpu/o3/ |
| H A D | lsq_unit.hh | 408 typename LoadQueue::iterator idx; member in class:LSQUnit::LQSenderState
426 typename StoreQueue::iterator idx; member in class:LSQUnit::SQSenderState
[all...] |
| H A D | inst_queue_impl.hh | 839 int idx = FUPool::NoCapableFU; local
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| H A D | cpu.hh | 660 void activateStage(const StageIdx idx) argument
664 void deactivateStage(const StageIdx idx) argument
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| /gem5/src/dev/arm/ |
| H A D | gic_v3_its.cc | 1108 Gicv3Its::getPort(const std::string &if_name, PortID idx) argument
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| H A D | gic_v3_cpu_interface.cc | 2109 int idx = -1; local
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| /gem5/src/arch/arm/ |
| H A D | table_walker.cc | 118 TableWalker::getPort(const std::string &if_name, PortID idx) argument
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| /gem5/src/cpu/ |
| H A D | base_dyn_inst.hh | 387 void renameDestReg(int idx, argument
401 renameSrcReg(int idx, PhysRegIdPtr renamed_src) argument
409 flattenDestReg(int idx, const RegId& flattened_dest) argument
671 setIntRegOperand(const StaticInst *si, int idx, RegVal val) argument
677 setCCRegOperand(const StaticInst *si, int idx, RegVal val) argument
683 setVecRegOperand(const StaticInst *si, int idx, const VecRegContainer& val) argument
691 setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val) argument
697 setVecElemOperand(const StaticInst *si, int idx, const VecElem val) argument
703 setVecPredRegOperand(const StaticInst *si, int idx, const VecPredRegContainer& val) argument
[all...] |