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14184:11ac1337c5e2 |
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16-Aug-2019 |
Gabe Black <gabeblack@google.com> |
mem: Move ruby protocols into a directory called ruby_protocol.
Now that the gem5 protocols are split out, it would be nice to put them in their own protocol directory. It's also confusing to have files called *_protocol which are not in the protocol directory.
Change-Id: I7475ee111630050a2421816dfd290921baab9f71 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20230 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
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11308:7d8836fd043d |
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19-Jan-2016 |
Tony Gutierrez <anthony.gutierrez@amd.com> |
gpu-compute: AMD's baseline GPU model
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11168:f98eb2da15a4 |
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12-Oct-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
misc: Remove redundant compiler-specific defines
This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap (and similar) abstractions, as these are no longer needed with gcc 4.7 and clang 3.1 as minimum compiler versions.
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11087:3c4bda5a2f66 |
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05-Sep-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: call setMRU from L1 controllers, not from sequencer Currently the sequencer calls the function setMRU that updates the replacement policy structures with the first level caches. While functionally this is correct, the problem is that this requires calling findTagInSet() which is an expensive function. This patch removes the calls to setMRU from the sequencer. All controllers should now update the replacement policy on their own.
The set and the way index for a given cache entry can be found within the AbstractCacheEntry structure. Use these indicies to update the replacement policy structures.
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11061:25b53a7195f7 |
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29-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: eliminate type uint64 and int64 These types are being replaced with uint64_t and int64_t.
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11059:40e622551656 |
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27-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: handle llsc accesses through CacheEntry, not CacheMemory
The sequencer takes care of llsc accesses by calling upon functions from the CacheMemory. This is unnecessary once the required CacheEntry object is available. Thus some of the calls to findTagInSet() are avoided.
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11049:dfb0aa3f0649 |
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19-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: reverts to changeset: bf82f1f7b040
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11034:a89984ca7d15 |
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14-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: cache memory: drop {try,test}CacheAccess functions
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11033:9a0022457323 |
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14-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: call setMRU from L1 controllers, not from sequencer Currently the sequencer calls the function setMRU that updates the replacement policy structures with the first level caches. While functionally this is correct, the problem is that this requires calling findTagInSet() which is an expensive function. This patch removes the calls to setMRU from the sequencer. All controllers should now update the replacement policy on their own.
The set and the way index for a given cache entry can be found within the AbstractCacheEntry structure. Use these indicies to update the replacement policy structures.
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11031:3815437cb231 |
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14-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: eliminate type uint64 and int64
These types are being replaced with uint64_t and int64_t.
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11027:bf82f1f7b040 |
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14-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: handle llsc accesses through CacheEntry, not CacheMemory
The sequencer takes care of llsc accesses by calling upon functions from the CacheMemory. This is unnecessary once the required CacheEntry object is available. Thus some of the calls to findTagInSet() are avoided.
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11025:4872dbdea907 |
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14-Aug-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: replace Address by Addr This patch eliminates the type Address defined by the ruby memory system. This memory system would now use the type Addr that is in use by the rest of the system.
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11019:fc1e41e88fd3 |
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14-Aug-2015 |
Joel Hestness <jthestness@gmail.com> |
ruby: Remove the RubyCache/CacheMemory latency
The RubyCache (CacheMemory) latency parameter is only used for top-level caches instantiated for Ruby coherence protocols. However, the top-level cache hit latency is assessed by the Sequencer as accesses flow through to the cache hierarchy. Further, protocol state machines should be enforcing these cache hit latencies, but RubyCaches do not expose their latency to any existng state machines through the SLICC/C++ interface. Thus, the RubyCache latency parameter is superfluous for all caches. This is confusing for users.
As a step toward pushing L0/L1 cache hit latency into the top-level cache controllers, move their latencies out of the RubyCache declarations and over to their Sequencers. Eventually, these Sequencer parameters should be exposed as parameters to the top-level cache controllers, which should assess the latency. NOTE: Assessing these latencies in the cache controllers will require modifying each to eliminate instantaneous Ruby hit callbacks in transitions that finish accesses, which is likely a large undertaking.
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10980:7de6f95a0817 |
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20-Jul-2015 |
David Hashe <david.hashe@amd.com> |
ruby: expose access permission to replacement policies
This patch adds support that allows the replacement policy to identify each cache block's access permission. This information can be useful when making replacement decisions.
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10978:436d5dde4bb7 |
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20-Jul-2015 |
David Hashe <david.hashe@amd.com> |
ruby: fix deadlock bug in banked array resource checks
The Ruby banked array resource checks (initiated from SLICC) did a check and allocate at the same time. If a transition needs more than one resource, then it might check/allocate resource #1, then fail to get resource #2. Another transition might then try to get the same resources, but in reverse order. Deadlock.
This patch separates resource checking and resource reservation into two steps to avoid deadlock.
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10974:bbdf1177f250 |
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20-Jul-2015 |
David Hashe <david.hashe@amd.com> |
ruby: allocate a block in CacheMemory without updating LRU state
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10973:4820cc8408b0 |
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20-Jul-2015 |
David Hashe <david.hashe@amd.com> |
ruby: speed up function used for cache walks
This patch adds a few helpful functions that allow .sm files to directly invalidate all cache blocks using a trigger queue rather than rely on each individual cache block to be invalidated via requests from the mandatory queue.
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10970:ea8bdb1d9f1e |
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20-Jul-2015 |
David Hashe <david.hashe@amd.com> |
ruby: initialize replacement policies with their own simobjs
this is in preparation for other replacement policies that take additional parameters.
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10969:a588fceeb834 |
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20-Jul-2015 |
David Hashe <david.hashe@amd.com> |
ruby: give access to cache tag/data latencies from SLICC
This patch exposes the tag and data array latencies to the SLICC state machines so that it can be used to determine the correct enqueue latency for response messages.
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10441:5377550e1e15 |
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11-Oct-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: structures: coorect #ifndef macros in header files
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10314:94b6b28fc968 |
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01-Sep-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: remove typedef of Index as int64 The Index type defined as typedef int64 does not really provide any help since in most places we use primitive types instead of Index. Also, the name Index is very generic that it does not merit being used as a typename.
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10301:44839e8febbd |
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01-Sep-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: move files from ruby/system to ruby/structures
The directory ruby/system is crowded and unorganized. Hence, the files the hold actual physical structures, are being moved to the directory ruby/structures. This includes Cache Memory, Directory Memory, Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table, Bank Array.
The directory ruby/systems has the glue code that holds these structures together.
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