CacheMemory.hh revision 11059:40e622551656
17404SAli.Saidi@ARM.com/* 212709Sgiacomo.travaglini@arm.com * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood 37404SAli.Saidi@ARM.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47404SAli.Saidi@ARM.com * All rights reserved. 57404SAli.Saidi@ARM.com * 67404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 77404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 87404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 97404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 107404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 117404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 127404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 137404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 147404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 157404SAli.Saidi@ARM.com * this software without specific prior written permission. 167404SAli.Saidi@ARM.com * 177404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 187404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 197404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 207404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 217404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 227404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 237404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 247404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 257404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 267404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 277404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 287404SAli.Saidi@ARM.com */ 297404SAli.Saidi@ARM.com 307404SAli.Saidi@ARM.com#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 317404SAli.Saidi@ARM.com#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 327404SAli.Saidi@ARM.com 337404SAli.Saidi@ARM.com#include <string> 347404SAli.Saidi@ARM.com#include <vector> 357404SAli.Saidi@ARM.com 367404SAli.Saidi@ARM.com#include "base/hashmap.hh" 377404SAli.Saidi@ARM.com#include "base/statistics.hh" 3810037SARM gem5 Developers#include "mem/protocol/CacheRequestType.hh" 397404SAli.Saidi@ARM.com#include "mem/protocol/CacheResourceType.hh" 4010873Sandreas.sandberg@arm.com#include "mem/protocol/RubyRequest.hh" 417404SAli.Saidi@ARM.com#include "mem/ruby/common/DataBlock.hh" 4210474Sandreas.hansson@arm.com#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh" 4310474Sandreas.hansson@arm.com#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh" 447404SAli.Saidi@ARM.com#include "mem/ruby/structures/AbstractReplacementPolicy.hh" 4510037SARM gem5 Developers#include "mem/ruby/structures/BankedArray.hh" 4610037SARM gem5 Developers#include "mem/ruby/system/CacheRecorder.hh" 477404SAli.Saidi@ARM.com#include "params/RubyCache.hh" 487728SAli.Saidi@ARM.com#include "sim/sim_object.hh" 497404SAli.Saidi@ARM.com 508245Snate@binkert.orgclass CacheMemory : public SimObject 519152Satgutier@umich.edu{ 528245Snate@binkert.org public: 538245Snate@binkert.org typedef RubyCacheParams Params; 5410873Sandreas.sandberg@arm.com CacheMemory(const Params *p); 557748SAli.Saidi@ARM.com ~CacheMemory(); 567404SAli.Saidi@ARM.com 577404SAli.Saidi@ARM.com void init(); 587404SAli.Saidi@ARM.com 597404SAli.Saidi@ARM.com // Public Methods 6010913Sandreas.sandberg@arm.com // perform a cache access and see if we hit or not. Return true on a hit. 6110717Sandreas.hansson@arm.com bool tryCacheAccess(Addr address, RubyRequestType type, 6210717Sandreas.hansson@arm.com DataBlock*& data_ptr); 6310717Sandreas.hansson@arm.com 649258SAli.Saidi@ARM.com // similar to above, but doesn't require full access check 6510621SCurtis.Dunham@arm.com bool testCacheAccess(Addr address, RubyRequestType type, 6610621SCurtis.Dunham@arm.com DataBlock*& data_ptr); 6712086Sspwilson2@wisc.edu 6812086Sspwilson2@wisc.edu // tests to see if an address is present in the cache 6912086Sspwilson2@wisc.edu bool isTagPresent(Addr address) const; 7012086Sspwilson2@wisc.edu 7112086Sspwilson2@wisc.edu // Returns true if there is: 7212086Sspwilson2@wisc.edu // a) a tag match on this address or there is 7311588SCurtis.Dunham@arm.com // b) an unused line in the same cache "way" 7411588SCurtis.Dunham@arm.com bool cacheAvail(Addr address) const; 7512086Sspwilson2@wisc.edu 767439Sdam.sunwoo@arm.com // find an unused entry and sets the tag appropriate for the address 777576SAli.Saidi@ARM.com AbstractCacheEntry* allocate(Addr address, 7810037SARM gem5 Developers AbstractCacheEntry* new_entry, bool touch); 7910037SARM gem5 Developers AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry) 8010037SARM gem5 Developers { 8110717Sandreas.hansson@arm.com return allocate(address, new_entry, true); 8210037SARM gem5 Developers } 8310037SARM gem5 Developers void allocateVoid(Addr address, AbstractCacheEntry* new_entry) 8410037SARM gem5 Developers { 8510037SARM gem5 Developers allocate(address, new_entry, true); 8610037SARM gem5 Developers } 8710037SARM gem5 Developers 8810037SARM gem5 Developers // Explicitly free up this address 8910037SARM gem5 Developers void deallocate(Addr address); 9010037SARM gem5 Developers 9110037SARM gem5 Developers // Returns with the physical address of the conflicting cache line 9210037SARM gem5 Developers Addr cacheProbe(Addr address) const; 9310037SARM gem5 Developers 947439Sdam.sunwoo@arm.com // looks an address up in the cache 957404SAli.Saidi@ARM.com AbstractCacheEntry* lookup(Addr address); 967404SAli.Saidi@ARM.com const AbstractCacheEntry* lookup(Addr address) const; 977404SAli.Saidi@ARM.com 987404SAli.Saidi@ARM.com Cycles getTagLatency() const { return tagArray.getLatency(); } 997404SAli.Saidi@ARM.com Cycles getDataLatency() const { return dataArray.getLatency(); } 1007404SAli.Saidi@ARM.com 10110717Sandreas.hansson@arm.com bool isBlockInvalid(int64 cache_set, int64 loc); 10210717Sandreas.hansson@arm.com bool isBlockNotBusy(int64 cache_set, int64 loc); 10310717Sandreas.hansson@arm.com 10410717Sandreas.hansson@arm.com // Hook for checkpointing the contents of the cache 10510717Sandreas.hansson@arm.com void recordCacheContents(int cntrl, CacheRecorder* tr) const; 10610717Sandreas.hansson@arm.com 10710717Sandreas.hansson@arm.com // Set this address to most recently used 10810717Sandreas.hansson@arm.com void setMRU(Addr address); 10910717Sandreas.hansson@arm.com 11010717Sandreas.hansson@arm.com // Functions for locking and unlocking cache lines corresponding to the 11110717Sandreas.hansson@arm.com // provided address. These are required for supporting atomic memory 11210717Sandreas.hansson@arm.com // accesses. These are to be used when only the address of the cache entry 11310717Sandreas.hansson@arm.com // is available. In case the entry itself is available. use the functions 11410717Sandreas.hansson@arm.com // provided by the AbstractCacheEntry class. 11510717Sandreas.hansson@arm.com void setLocked (Addr addr, int context); 11610717Sandreas.hansson@arm.com void clearLocked (Addr addr); 11710717Sandreas.hansson@arm.com bool isLocked (Addr addr, int context); 11810717Sandreas.hansson@arm.com 11910717Sandreas.hansson@arm.com // Print cache contents 12010717Sandreas.hansson@arm.com void print(std::ostream& out) const; 12110717Sandreas.hansson@arm.com void printData(std::ostream& out) const; 12210717Sandreas.hansson@arm.com 12310717Sandreas.hansson@arm.com void regStats(); 12410717Sandreas.hansson@arm.com bool checkResourceAvailable(CacheResourceType res, Addr addr); 12510717Sandreas.hansson@arm.com void recordRequestType(CacheRequestType requestType, Addr addr); 12610717Sandreas.hansson@arm.com 12710717Sandreas.hansson@arm.com public: 12810717Sandreas.hansson@arm.com Stats::Scalar m_demand_hits; 12910717Sandreas.hansson@arm.com Stats::Scalar m_demand_misses; 13010537Sandreas.hansson@arm.com Stats::Formula m_demand_accesses; 13110537Sandreas.hansson@arm.com 13210537Sandreas.hansson@arm.com Stats::Scalar m_sw_prefetches; 13310537Sandreas.hansson@arm.com Stats::Scalar m_hw_prefetches; 13410537Sandreas.hansson@arm.com Stats::Formula m_prefetches; 13512738Sandreas.sandberg@arm.com 13610537Sandreas.hansson@arm.com Stats::Vector m_accessModeType; 13710537Sandreas.hansson@arm.com 13810537Sandreas.hansson@arm.com Stats::Scalar numDataArrayReads; 13910037SARM gem5 Developers Stats::Scalar numDataArrayWrites; 14010037SARM gem5 Developers Stats::Scalar numTagArrayReads; 14110037SARM gem5 Developers Stats::Scalar numTagArrayWrites; 1429152Satgutier@umich.edu 1439152Satgutier@umich.edu Stats::Scalar numTagArrayStalls; 1449152Satgutier@umich.edu Stats::Scalar numDataArrayStalls; 14510913Sandreas.sandberg@arm.com 14611588SCurtis.Dunham@arm.com int getCacheSize() const { return m_cache_size; } 14711588SCurtis.Dunham@arm.com int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; } 1489152Satgutier@umich.edu Addr getAddressAtIdx(int idx) const; 14910913Sandreas.sandberg@arm.com 1509152Satgutier@umich.edu private: 15110913Sandreas.sandberg@arm.com // convert a Address to its location in the cache 1529152Satgutier@umich.edu int64 addressToCacheSet(Addr address) const; 1539152Satgutier@umich.edu 1549152Satgutier@umich.edu // Given a cache tag: returns the index of the tag in a set. 15510913Sandreas.sandberg@arm.com // returns -1 if the tag is not found. 15610913Sandreas.sandberg@arm.com int findTagInSet(int64 line, Addr tag) const; 1577404SAli.Saidi@ARM.com int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const; 15810037SARM gem5 Developers 1599152Satgutier@umich.edu // Private copy constructor and assignment operator 16010037SARM gem5 Developers CacheMemory(const CacheMemory& obj); 16110037SARM gem5 Developers CacheMemory& operator=(const CacheMemory& obj); 16210037SARM gem5 Developers 16310037SARM gem5 Developers private: 16410037SARM gem5 Developers // Data Members (m_prefix) 16510037SARM gem5 Developers bool m_is_instruction_only_cache; 16610037SARM gem5 Developers 16710037SARM gem5 Developers // The first index is the # of cache lines. 1689152Satgutier@umich.edu // The second index is the the amount associativity. 16910913Sandreas.sandberg@arm.com m5::hash_map<Addr, int> m_tag_index; 17010037SARM gem5 Developers std::vector<std::vector<AbstractCacheEntry*> > m_cache; 17110037SARM gem5 Developers 17210913Sandreas.sandberg@arm.com AbstractReplacementPolicy *m_replacementPolicy_ptr; 1737733SAli.Saidi@ARM.com 1747404SAli.Saidi@ARM.com BankedArray dataArray; 1757404SAli.Saidi@ARM.com BankedArray tagArray; 1767748SAli.Saidi@ARM.com 1779342SAndreas.Sandberg@arm.com int m_cache_size; 1787748SAli.Saidi@ARM.com int m_cache_num_sets; 1799524SAndreas.Sandberg@ARM.com int m_cache_num_set_bits; 1809152Satgutier@umich.edu int m_cache_assoc; 1819152Satgutier@umich.edu int m_start_index_bit; 18210621SCurtis.Dunham@arm.com bool m_resource_stalls; 1837748SAli.Saidi@ARM.com}; 1847748SAli.Saidi@ARM.com 1857748SAli.Saidi@ARM.comstd::ostream& operator<<(std::ostream& out, const CacheMemory& obj); 1867404SAli.Saidi@ARM.com 18712749Sgiacomo.travaglini@arm.com#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__ 18810037SARM gem5 Developers