CacheMemory.hh revision 10301:44839e8febbd 
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
30#define __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
31
32#include <string>
33#include <vector>
34
35#include "base/hashmap.hh"
36#include "base/statistics.hh"
37#include "mem/protocol/CacheRequestType.hh"
38#include "mem/protocol/CacheResourceType.hh"
39#include "mem/protocol/RubyRequest.hh"
40#include "mem/ruby/common/DataBlock.hh"
41#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
42#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
43#include "mem/ruby/structures/BankedArray.hh"
44#include "mem/ruby/structures/LRUPolicy.hh"
45#include "mem/ruby/structures/PseudoLRUPolicy.hh"
46#include "mem/ruby/system/CacheRecorder.hh"
47#include "params/RubyCache.hh"
48#include "sim/sim_object.hh"
49
50class CacheMemory : public SimObject
51{
52  public:
53    typedef RubyCacheParams Params;
54    CacheMemory(const Params *p);
55    ~CacheMemory();
56
57    void init();
58
59    // Public Methods
60    // perform a cache access and see if we hit or not.  Return true on a hit.
61    bool tryCacheAccess(const Address& address, RubyRequestType type,
62                        DataBlock*& data_ptr);
63
64    // similar to above, but doesn't require full access check
65    bool testCacheAccess(const Address& address, RubyRequestType type,
66                         DataBlock*& data_ptr);
67
68    // tests to see if an address is present in the cache
69    bool isTagPresent(const Address& address) const;
70
71    // Returns true if there is:
72    //   a) a tag match on this address or there is
73    //   b) an unused line in the same cache "way"
74    bool cacheAvail(const Address& address) const;
75
76    // find an unused entry and sets the tag appropriate for the address
77    AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
78    void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
79    {
80        allocate(address, new_entry);
81    }
82
83    // Explicitly free up this address
84    void deallocate(const Address& address);
85
86    // Returns with the physical address of the conflicting cache line
87    Address cacheProbe(const Address& address) const;
88
89    // looks an address up in the cache
90    AbstractCacheEntry* lookup(const Address& address);
91    const AbstractCacheEntry* lookup(const Address& address) const;
92
93    Cycles getLatency() const { return m_latency; }
94
95    // Hook for checkpointing the contents of the cache
96    void recordCacheContents(int cntrl, CacheRecorder* tr) const;
97
98    // Set this address to most recently used
99    void setMRU(const Address& address);
100
101    void setLocked (const Address& addr, int context);
102    void clearLocked (const Address& addr);
103    bool isLocked (const Address& addr, int context);
104
105    // Print cache contents
106    void print(std::ostream& out) const;
107    void printData(std::ostream& out) const;
108
109    void regStats();
110    bool checkResourceAvailable(CacheResourceType res, Address addr);
111    void recordRequestType(CacheRequestType requestType);
112
113  public:
114    Stats::Scalar m_demand_hits;
115    Stats::Scalar m_demand_misses;
116    Stats::Formula m_demand_accesses;
117
118    Stats::Scalar m_sw_prefetches;
119    Stats::Scalar m_hw_prefetches;
120    Stats::Formula m_prefetches;
121
122    Stats::Vector m_accessModeType;
123
124    Stats::Scalar numDataArrayReads;
125    Stats::Scalar numDataArrayWrites;
126    Stats::Scalar numTagArrayReads;
127    Stats::Scalar numTagArrayWrites;
128
129    Stats::Scalar numTagArrayStalls;
130    Stats::Scalar numDataArrayStalls;
131
132  private:
133    // convert a Address to its location in the cache
134    Index addressToCacheSet(const Address& address) const;
135
136    // Given a cache tag: returns the index of the tag in a set.
137    // returns -1 if the tag is not found.
138    int findTagInSet(Index line, const Address& tag) const;
139    int findTagInSetIgnorePermissions(Index cacheSet,
140                                      const Address& tag) const;
141
142    // Private copy constructor and assignment operator
143    CacheMemory(const CacheMemory& obj);
144    CacheMemory& operator=(const CacheMemory& obj);
145
146  private:
147    Cycles m_latency;
148
149    // Data Members (m_prefix)
150    bool m_is_instruction_only_cache;
151
152    // The first index is the # of cache lines.
153    // The second index is the the amount associativity.
154    m5::hash_map<Address, int> m_tag_index;
155    std::vector<std::vector<AbstractCacheEntry*> > m_cache;
156
157    AbstractReplacementPolicy *m_replacementPolicy_ptr;
158
159    BankedArray dataArray;
160    BankedArray tagArray;
161
162    int m_cache_size;
163    std::string m_policy;
164    int m_cache_num_sets;
165    int m_cache_num_set_bits;
166    int m_cache_assoc;
167    int m_start_index_bit;
168    bool m_resource_stalls;
169};
170
171std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
172
173#endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
174