CacheMemory.hh revision 11168:f98eb2da15a4 
1/*
2 * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30#ifndef __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
31#define __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
32
33#include <string>
34#include <unordered_map>
35#include <vector>
36
37#include "base/statistics.hh"
38#include "mem/protocol/CacheRequestType.hh"
39#include "mem/protocol/CacheResourceType.hh"
40#include "mem/protocol/RubyRequest.hh"
41#include "mem/ruby/common/DataBlock.hh"
42#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
43#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
44#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
45#include "mem/ruby/structures/BankedArray.hh"
46#include "mem/ruby/system/CacheRecorder.hh"
47#include "params/RubyCache.hh"
48#include "sim/sim_object.hh"
49
50class CacheMemory : public SimObject
51{
52  public:
53    typedef RubyCacheParams Params;
54    CacheMemory(const Params *p);
55    ~CacheMemory();
56
57    void init();
58
59    // Public Methods
60    // perform a cache access and see if we hit or not.  Return true on a hit.
61    bool tryCacheAccess(Addr address, RubyRequestType type,
62                        DataBlock*& data_ptr);
63
64    // similar to above, but doesn't require full access check
65    bool testCacheAccess(Addr address, RubyRequestType type,
66                         DataBlock*& data_ptr);
67
68    // tests to see if an address is present in the cache
69    bool isTagPresent(Addr address) const;
70
71    // Returns true if there is:
72    //   a) a tag match on this address or there is
73    //   b) an unused line in the same cache "way"
74    bool cacheAvail(Addr address) const;
75
76    // find an unused entry and sets the tag appropriate for the address
77    AbstractCacheEntry* allocate(Addr address,
78                                 AbstractCacheEntry* new_entry, bool touch);
79    AbstractCacheEntry* allocate(Addr address, AbstractCacheEntry* new_entry)
80    {
81        return allocate(address, new_entry, true);
82    }
83    void allocateVoid(Addr address, AbstractCacheEntry* new_entry)
84    {
85        allocate(address, new_entry, true);
86    }
87
88    // Explicitly free up this address
89    void deallocate(Addr address);
90
91    // Returns with the physical address of the conflicting cache line
92    Addr cacheProbe(Addr address) const;
93
94    // looks an address up in the cache
95    AbstractCacheEntry* lookup(Addr address);
96    const AbstractCacheEntry* lookup(Addr address) const;
97
98    Cycles getTagLatency() const { return tagArray.getLatency(); }
99    Cycles getDataLatency() const { return dataArray.getLatency(); }
100
101    bool isBlockInvalid(int64_t cache_set, int64_t loc);
102    bool isBlockNotBusy(int64_t cache_set, int64_t loc);
103
104    // Hook for checkpointing the contents of the cache
105    void recordCacheContents(int cntrl, CacheRecorder* tr) const;
106
107    // Set this address to most recently used
108    void setMRU(Addr address);
109    // Set this entry to most recently used
110    void setMRU(const AbstractCacheEntry *e);
111
112    // Functions for locking and unlocking cache lines corresponding to the
113    // provided address.  These are required for supporting atomic memory
114    // accesses.  These are to be used when only the address of the cache entry
115    // is available.  In case the entry itself is available. use the functions
116    // provided by the AbstractCacheEntry class.
117    void setLocked (Addr addr, int context);
118    void clearLocked (Addr addr);
119    bool isLocked (Addr addr, int context);
120
121    // Print cache contents
122    void print(std::ostream& out) const;
123    void printData(std::ostream& out) const;
124
125    void regStats();
126    bool checkResourceAvailable(CacheResourceType res, Addr addr);
127    void recordRequestType(CacheRequestType requestType, Addr addr);
128
129  public:
130    Stats::Scalar m_demand_hits;
131    Stats::Scalar m_demand_misses;
132    Stats::Formula m_demand_accesses;
133
134    Stats::Scalar m_sw_prefetches;
135    Stats::Scalar m_hw_prefetches;
136    Stats::Formula m_prefetches;
137
138    Stats::Vector m_accessModeType;
139
140    Stats::Scalar numDataArrayReads;
141    Stats::Scalar numDataArrayWrites;
142    Stats::Scalar numTagArrayReads;
143    Stats::Scalar numTagArrayWrites;
144
145    Stats::Scalar numTagArrayStalls;
146    Stats::Scalar numDataArrayStalls;
147
148    int getCacheSize() const { return m_cache_size; }
149    int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; }
150    Addr getAddressAtIdx(int idx) const;
151
152  private:
153    // convert a Address to its location in the cache
154    int64_t addressToCacheSet(Addr address) const;
155
156    // Given a cache tag: returns the index of the tag in a set.
157    // returns -1 if the tag is not found.
158    int findTagInSet(int64_t line, Addr tag) const;
159    int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const;
160
161    // Private copy constructor and assignment operator
162    CacheMemory(const CacheMemory& obj);
163    CacheMemory& operator=(const CacheMemory& obj);
164
165  private:
166    // Data Members (m_prefix)
167    bool m_is_instruction_only_cache;
168
169    // The first index is the # of cache lines.
170    // The second index is the the amount associativity.
171    std::unordered_map<Addr, int> m_tag_index;
172    std::vector<std::vector<AbstractCacheEntry*> > m_cache;
173
174    AbstractReplacementPolicy *m_replacementPolicy_ptr;
175
176    BankedArray dataArray;
177    BankedArray tagArray;
178
179    int m_cache_size;
180    int m_cache_num_sets;
181    int m_cache_num_set_bits;
182    int m_cache_assoc;
183    int m_start_index_bit;
184    bool m_resource_stalls;
185};
186
187std::ostream& operator<<(std::ostream& out, const CacheMemory& obj);
188
189#endif // __MEM_RUBY_STRUCTURES_CACHEMEMORY_HH__
190