base.cc revision 2012 
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include <cmath>
30#include <cstdio>
31#include <cstdlib>
32#include <iostream>
33#include <iomanip>
34#include <list>
35#include <sstream>
36#include <string>
37
38#include "base/cprintf.hh"
39#include "base/inifile.hh"
40#include "base/loader/symtab.hh"
41#include "base/misc.hh"
42#include "base/pollevent.hh"
43#include "base/range.hh"
44#include "base/stats/events.hh"
45#include "base/trace.hh"
46#include "cpu/base.hh"
47#include "cpu/exec_context.hh"
48#include "cpu/exetrace.hh"
49#include "cpu/profile.hh"
50#include "cpu/sampler/sampler.hh"
51#include "cpu/simple/cpu.hh"
52#include "cpu/smt.hh"
53#include "cpu/static_inst.hh"
54#include "kern/kernel_stats.hh"
55#include "mem/base_mem.hh"
56#include "mem/mem_interface.hh"
57#include "sim/builder.hh"
58#include "sim/debug.hh"
59#include "sim/host.hh"
60#include "sim/sim_events.hh"
61#include "sim/sim_object.hh"
62#include "sim/stats.hh"
63
64#if FULL_SYSTEM
65#include "base/remote_gdb.hh"
66#include "mem/functional/memory_control.hh"
67#include "mem/functional/physical.hh"
68#include "sim/system.hh"
69#include "targetarch/alpha_memory.hh"
70#include "targetarch/stacktrace.hh"
71#include "targetarch/vtophys.hh"
72#else // !FULL_SYSTEM
73#include "mem/functional/functional.hh"
74#endif // FULL_SYSTEM
75
76using namespace std;
77
78
79SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
80    : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
81{
82}
83
84void
85SimpleCPU::TickEvent::process()
86{
87    int count = width;
88    do {
89        cpu->tick();
90    } while (--count > 0 && cpu->status() == Running);
91}
92
93const char *
94SimpleCPU::TickEvent::description()
95{
96    return "SimpleCPU tick event";
97}
98
99
100SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
101    : Event(&mainEventQueue), cpu(_cpu)
102{
103}
104
105void SimpleCPU::CacheCompletionEvent::process()
106{
107    cpu->processCacheCompletion();
108}
109
110const char *
111SimpleCPU::CacheCompletionEvent::description()
112{
113    return "SimpleCPU cache completion event";
114}
115
116SimpleCPU::SimpleCPU(Params *p)
117    : BaseCPU(p), tickEvent(this, p->width), xc(NULL),
118      cacheCompletionEvent(this)
119{
120    _status = Idle;
121#if FULL_SYSTEM
122    xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
123
124    // initialize CPU, including PC
125    TheISA::initCPU(&xc->regs);
126#else
127    xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
128#endif // !FULL_SYSTEM
129
130    icacheInterface = p->icache_interface;
131    dcacheInterface = p->dcache_interface;
132
133    memReq = new MemReq();
134    memReq->xc = xc;
135    memReq->asid = 0;
136    memReq->data = new uint8_t[64];
137
138    numInst = 0;
139    startNumInst = 0;
140    numLoad = 0;
141    startNumLoad = 0;
142    lastIcacheStall = 0;
143    lastDcacheStall = 0;
144
145    execContexts.push_back(xc);
146}
147
148SimpleCPU::~SimpleCPU()
149{
150}
151
152void
153SimpleCPU::switchOut(Sampler *s)
154{
155    sampler = s;
156    if (status() == DcacheMissStall) {
157        DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n");
158        _status = DcacheMissSwitch;
159    }
160    else {
161        _status = SwitchedOut;
162
163        if (tickEvent.scheduled())
164            tickEvent.squash();
165
166        sampler->signalSwitched();
167    }
168}
169
170
171void
172SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
173{
174    BaseCPU::takeOverFrom(oldCPU);
175
176    assert(!tickEvent.scheduled());
177
178    // if any of this CPU's ExecContexts are active, mark the CPU as
179    // running and schedule its tick event.
180    for (int i = 0; i < execContexts.size(); ++i) {
181        ExecContext *xc = execContexts[i];
182        if (xc->status() == ExecContext::Active && _status != Running) {
183            _status = Running;
184            tickEvent.schedule(curTick);
185        }
186    }
187}
188
189
190void
191SimpleCPU::activateContext(int thread_num, int delay)
192{
193    assert(thread_num == 0);
194    assert(xc);
195
196    assert(_status == Idle);
197    notIdleFraction++;
198    scheduleTickEvent(delay);
199    _status = Running;
200}
201
202
203void
204SimpleCPU::suspendContext(int thread_num)
205{
206    assert(thread_num == 0);
207    assert(xc);
208
209    assert(_status == Running);
210    notIdleFraction--;
211    unscheduleTickEvent();
212    _status = Idle;
213}
214
215
216void
217SimpleCPU::deallocateContext(int thread_num)
218{
219    // for now, these are equivalent
220    suspendContext(thread_num);
221}
222
223
224void
225SimpleCPU::haltContext(int thread_num)
226{
227    // for now, these are equivalent
228    suspendContext(thread_num);
229}
230
231
232void
233SimpleCPU::regStats()
234{
235    using namespace Stats;
236
237    BaseCPU::regStats();
238
239    numInsts
240        .name(name() + ".num_insts")
241        .desc("Number of instructions executed")
242        ;
243
244    numMemRefs
245        .name(name() + ".num_refs")
246        .desc("Number of memory references")
247        ;
248
249    notIdleFraction
250        .name(name() + ".not_idle_fraction")
251        .desc("Percentage of non-idle cycles")
252        ;
253
254    idleFraction
255        .name(name() + ".idle_fraction")
256        .desc("Percentage of idle cycles")
257        ;
258
259    icacheStallCycles
260        .name(name() + ".icache_stall_cycles")
261        .desc("ICache total stall cycles")
262        .prereq(icacheStallCycles)
263        ;
264
265    dcacheStallCycles
266        .name(name() + ".dcache_stall_cycles")
267        .desc("DCache total stall cycles")
268        .prereq(dcacheStallCycles)
269        ;
270
271    idleFraction = constant(1.0) - notIdleFraction;
272}
273
274void
275SimpleCPU::resetStats()
276{
277    startNumInst = numInst;
278    notIdleFraction = (_status != Idle);
279}
280
281void
282SimpleCPU::serialize(ostream &os)
283{
284    BaseCPU::serialize(os);
285    SERIALIZE_ENUM(_status);
286    SERIALIZE_SCALAR(inst);
287    nameOut(os, csprintf("%s.xc", name()));
288    xc->serialize(os);
289    nameOut(os, csprintf("%s.tickEvent", name()));
290    tickEvent.serialize(os);
291    nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
292    cacheCompletionEvent.serialize(os);
293}
294
295void
296SimpleCPU::unserialize(Checkpoint *cp, const string &section)
297{
298    BaseCPU::unserialize(cp, section);
299    UNSERIALIZE_ENUM(_status);
300    UNSERIALIZE_SCALAR(inst);
301    xc->unserialize(cp, csprintf("%s.xc", section));
302    tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
303    cacheCompletionEvent
304        .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
305}
306
307void
308change_thread_state(int thread_number, int activate, int priority)
309{
310}
311
312Fault
313SimpleCPU::copySrcTranslate(Addr src)
314{
315    static bool no_warn = true;
316    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
317    // Only support block sizes of 64 atm.
318    assert(blk_size == 64);
319    int offset = src & (blk_size - 1);
320
321    // Make sure block doesn't span page
322    if (no_warn &&
323        (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) &&
324        (src >> 40) != 0xfffffc) {
325        warn("Copied block source spans pages %x.", src);
326        no_warn = false;
327    }
328
329    memReq->reset(src & ~(blk_size - 1), blk_size);
330
331    // translate to physical address
332    Fault fault = xc->translateDataReadReq(memReq);
333
334    assert(fault != Alignment_Fault);
335
336    if (fault == No_Fault) {
337        xc->copySrcAddr = src;
338        xc->copySrcPhysAddr = memReq->paddr + offset;
339    } else {
340        xc->copySrcAddr = 0;
341        xc->copySrcPhysAddr = 0;
342    }
343    return fault;
344}
345
346Fault
347SimpleCPU::copy(Addr dest)
348{
349    static bool no_warn = true;
350    int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
351    // Only support block sizes of 64 atm.
352    assert(blk_size == 64);
353    uint8_t data[blk_size];
354    //assert(xc->copySrcAddr);
355    int offset = dest & (blk_size - 1);
356
357    // Make sure block doesn't span page
358    if (no_warn &&
359        (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) &&
360        (dest >> 40) != 0xfffffc) {
361        no_warn = false;
362        warn("Copied block destination spans pages %x. ", dest);
363    }
364
365    memReq->reset(dest & ~(blk_size -1), blk_size);
366    // translate to physical address
367    Fault fault = xc->translateDataWriteReq(memReq);
368
369    assert(fault != Alignment_Fault);
370
371    if (fault == No_Fault) {
372        Addr dest_addr = memReq->paddr + offset;
373        // Need to read straight from memory since we have more than 8 bytes.
374        memReq->paddr = xc->copySrcPhysAddr;
375        xc->mem->read(memReq, data);
376        memReq->paddr = dest_addr;
377        xc->mem->write(memReq, data);
378        if (dcacheInterface) {
379            memReq->cmd = Copy;
380            memReq->completionEvent = NULL;
381            memReq->paddr = xc->copySrcPhysAddr;
382            memReq->dest = dest_addr;
383            memReq->size = 64;
384            memReq->time = curTick;
385            memReq->flags &= ~INST_READ;
386            dcacheInterface->access(memReq);
387        }
388    }
389    return fault;
390}
391
392// precise architected memory state accessor macros
393template <class T>
394Fault
395SimpleCPU::read(Addr addr, T &data, unsigned flags)
396{
397    if (status() == DcacheMissStall || status() == DcacheMissSwitch) {
398        Fault fault = xc->read(memReq,data);
399
400        if (traceData) {
401            traceData->setAddr(addr);
402        }
403        return fault;
404    }
405
406    memReq->reset(addr, sizeof(T), flags);
407
408    // translate to physical address
409    Fault fault = xc->translateDataReadReq(memReq);
410
411    // if we have a cache, do cache access too
412    if (fault == No_Fault && dcacheInterface) {
413        memReq->cmd = Read;
414        memReq->completionEvent = NULL;
415        memReq->time = curTick;
416        memReq->flags &= ~INST_READ;
417        MemAccessResult result = dcacheInterface->access(memReq);
418
419        // Ugly hack to get an event scheduled *only* if the access is
420        // a miss.  We really should add first-class support for this
421        // at some point.
422        if (result != MA_HIT && dcacheInterface->doEvents()) {
423            memReq->completionEvent = &cacheCompletionEvent;
424            lastDcacheStall = curTick;
425            unscheduleTickEvent();
426            _status = DcacheMissStall;
427        } else {
428            // do functional access
429            fault = xc->read(memReq, data);
430
431        }
432    } else if(fault == No_Fault) {
433        // do functional access
434        fault = xc->read(memReq, data);
435
436    }
437
438    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
439        recordEvent("Uncached Read");
440
441    return fault;
442}
443
444#ifndef DOXYGEN_SHOULD_SKIP_THIS
445
446template
447Fault
448SimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
449
450template
451Fault
452SimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
453
454template
455Fault
456SimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
457
458template
459Fault
460SimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
461
462#endif //DOXYGEN_SHOULD_SKIP_THIS
463
464template<>
465Fault
466SimpleCPU::read(Addr addr, double &data, unsigned flags)
467{
468    return read(addr, *(uint64_t*)&data, flags);
469}
470
471template<>
472Fault
473SimpleCPU::read(Addr addr, float &data, unsigned flags)
474{
475    return read(addr, *(uint32_t*)&data, flags);
476}
477
478
479template<>
480Fault
481SimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
482{
483    return read(addr, (uint32_t&)data, flags);
484}
485
486
487template <class T>
488Fault
489SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
490{
491    memReq->reset(addr, sizeof(T), flags);
492
493    // translate to physical address
494    Fault fault = xc->translateDataWriteReq(memReq);
495
496    // do functional access
497    if (fault == No_Fault)
498        fault = xc->write(memReq, data);
499
500    if (fault == No_Fault && dcacheInterface) {
501        memReq->cmd = Write;
502        memcpy(memReq->data,(uint8_t *)&data,memReq->size);
503        memReq->completionEvent = NULL;
504        memReq->time = curTick;
505        memReq->flags &= ~INST_READ;
506        MemAccessResult result = dcacheInterface->access(memReq);
507
508        // Ugly hack to get an event scheduled *only* if the access is
509        // a miss.  We really should add first-class support for this
510        // at some point.
511        if (result != MA_HIT && dcacheInterface->doEvents()) {
512            memReq->completionEvent = &cacheCompletionEvent;
513            lastDcacheStall = curTick;
514            unscheduleTickEvent();
515            _status = DcacheMissStall;
516        }
517    }
518
519    if (res && (fault == No_Fault))
520        *res = memReq->result;
521
522    if (!dcacheInterface && (memReq->flags & UNCACHEABLE))
523        recordEvent("Uncached Write");
524
525    return fault;
526}
527
528
529#ifndef DOXYGEN_SHOULD_SKIP_THIS
530template
531Fault
532SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
533
534template
535Fault
536SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
537
538template
539Fault
540SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
541
542template
543Fault
544SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
545
546#endif //DOXYGEN_SHOULD_SKIP_THIS
547
548template<>
549Fault
550SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
551{
552    return write(*(uint64_t*)&data, addr, flags, res);
553}
554
555template<>
556Fault
557SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
558{
559    return write(*(uint32_t*)&data, addr, flags, res);
560}
561
562
563template<>
564Fault
565SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
566{
567    return write((uint32_t)data, addr, flags, res);
568}
569
570
571#if FULL_SYSTEM
572Addr
573SimpleCPU::dbg_vtophys(Addr addr)
574{
575    return vtophys(xc, addr);
576}
577#endif // FULL_SYSTEM
578
579void
580SimpleCPU::processCacheCompletion()
581{
582    switch (status()) {
583      case IcacheMissStall:
584        icacheStallCycles += curTick - lastIcacheStall;
585        _status = IcacheMissComplete;
586        scheduleTickEvent(1);
587        break;
588      case DcacheMissStall:
589        if (memReq->cmd.isRead()) {
590            curStaticInst->execute(this,traceData);
591            if (traceData)
592                traceData->finalize();
593        }
594        dcacheStallCycles += curTick - lastDcacheStall;
595        _status = Running;
596        scheduleTickEvent(1);
597        break;
598      case DcacheMissSwitch:
599        if (memReq->cmd.isRead()) {
600            curStaticInst->execute(this,traceData);
601            if (traceData)
602                traceData->finalize();
603        }
604        _status = SwitchedOut;
605        sampler->signalSwitched();
606      case SwitchedOut:
607        // If this CPU has been switched out due to sampling/warm-up,
608        // ignore any further status changes (e.g., due to cache
609        // misses outstanding at the time of the switch).
610        return;
611      default:
612        panic("SimpleCPU::processCacheCompletion: bad state");
613        break;
614    }
615}
616
617#if FULL_SYSTEM
618void
619SimpleCPU::post_interrupt(int int_num, int index)
620{
621    BaseCPU::post_interrupt(int_num, index);
622
623    if (xc->status() == ExecContext::Suspended) {
624                DPRINTF(IPI,"Suspended Processor awoke\n");
625        xc->activate();
626    }
627}
628#endif // FULL_SYSTEM
629
630/* start simulation, program loaded, processor precise state initialized */
631void
632SimpleCPU::tick()
633{
634    numCycles++;
635
636    traceData = NULL;
637
638    Fault fault = No_Fault;
639
640#if FULL_SYSTEM
641    if (checkInterrupts && check_interrupts() && !xc->inPalMode() &&
642        status() != IcacheMissComplete) {
643        int ipl = 0;
644        int summary = 0;
645        checkInterrupts = false;
646        IntReg *ipr = xc->regs.ipr;
647
648        if (xc->regs.ipr[TheISA::IPR_SIRR]) {
649            for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
650                 i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
651                if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
652                    // See table 4-19 of 21164 hardware reference
653                    ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
654                    summary |= (ULL(1) << i);
655                }
656            }
657        }
658
659        uint64_t interrupts = xc->cpu->intr_status();
660        for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
661            i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
662            if (interrupts & (ULL(1) << i)) {
663                // See table 4-19 of 21164 hardware reference
664                ipl = i;
665                summary |= (ULL(1) << i);
666            }
667        }
668
669        if (ipr[TheISA::IPR_ASTRR])
670            panic("asynchronous traps not implemented\n");
671
672        if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
673            ipr[TheISA::IPR_ISR] = summary;
674            ipr[TheISA::IPR_INTID] = ipl;
675            xc->ev5_trap(Interrupt_Fault);
676
677            DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
678                    ipr[TheISA::IPR_IPLR], ipl, summary);
679        }
680    }
681#endif
682
683    // maintain $r0 semantics
684    xc->regs.intRegFile[ZeroReg] = 0;
685#ifdef TARGET_ALPHA
686    xc->regs.floatRegFile.d[ZeroReg] = 0.0;
687#endif // TARGET_ALPHA
688
689    if (status() == IcacheMissComplete) {
690        // We've already fetched an instruction and were stalled on an
691        // I-cache miss.  No need to fetch it again.
692
693        // Set status to running; tick event will get rescheduled if
694        // necessary at end of tick() function.
695        _status = Running;
696    }
697    else {
698        // Try to fetch an instruction
699
700        // set up memory request for instruction fetch
701#if FULL_SYSTEM
702#define IFETCH_FLAGS(pc)	((pc) & 1) ? PHYSICAL : 0
703#else
704#define IFETCH_FLAGS(pc)	0
705#endif
706
707        memReq->cmd = Read;
708        memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
709                     IFETCH_FLAGS(xc->regs.pc));
710
711        fault = xc->translateInstReq(memReq);
712
713        if (fault == No_Fault)
714            fault = xc->mem->read(memReq, inst);
715
716        if (icacheInterface && fault == No_Fault) {
717            memReq->completionEvent = NULL;
718
719            memReq->time = curTick;
720            memReq->flags |= INST_READ;
721            MemAccessResult result = icacheInterface->access(memReq);
722
723            // Ugly hack to get an event scheduled *only* if the access is
724            // a miss.  We really should add first-class support for this
725            // at some point.
726            if (result != MA_HIT && icacheInterface->doEvents()) {
727                memReq->completionEvent = &cacheCompletionEvent;
728                lastIcacheStall = curTick;
729                unscheduleTickEvent();
730                _status = IcacheMissStall;
731                return;
732            }
733        }
734    }
735
736    // If we've got a valid instruction (i.e., no fault on instruction
737    // fetch), then execute it.
738    if (fault == No_Fault) {
739
740        // keep an instruction count
741        numInst++;
742        numInsts++;
743
744        // check for instruction-count-based events
745        comInstEventQueue[0]->serviceEvents(numInst);
746
747        // decode the instruction
748        inst = gtoh(inst);
749        curStaticInst = StaticInst<TheISA>::decode(inst);
750
751        traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst,
752                                         xc->regs.pc);
753
754#if FULL_SYSTEM
755        xc->setInst(inst);
756#endif // FULL_SYSTEM
757
758        xc->func_exe_inst++;
759
760        fault = curStaticInst->execute(this, traceData);
761
762#if FULL_SYSTEM
763        if (xc->fnbin) {
764            assert(xc->kernelStats);
765            system->kernelBinning->execute(xc, inst);
766        }
767
768        if (xc->profile) {
769            bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0;
770            xc->profilePC = usermode ? 1 : xc->regs.pc;
771            ProfileNode *node = xc->profile->consume(xc, inst);
772            if (node)
773                xc->profileNode = node;
774        }
775#endif
776
777        if (curStaticInst->isMemRef()) {
778            numMemRefs++;
779        }
780
781        if (curStaticInst->isLoad()) {
782            ++numLoad;
783            comLoadEventQueue[0]->serviceEvents(numLoad);
784        }
785
786        // If we have a dcache miss, then we can't finialize the instruction
787        // trace yet because we want to populate it with the data later
788        if (traceData &&
789                !(status() == DcacheMissStall && memReq->cmd.isRead())) {
790            traceData->finalize();
791        }
792
793        traceFunctions(xc->regs.pc);
794
795    }	// if (fault == No_Fault)
796
797    if (fault != No_Fault) {
798#if FULL_SYSTEM
799        xc->ev5_trap(fault);
800#else // !FULL_SYSTEM
801        fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
802#endif // FULL_SYSTEM
803    }
804    else {
805        // go to the next instruction
806        xc->regs.pc = xc->regs.npc;
807        xc->regs.npc += sizeof(MachInst);
808    }
809
810#if FULL_SYSTEM
811    Addr oldpc;
812    do {
813        oldpc = xc->regs.pc;
814        system->pcEventQueue.service(xc);
815    } while (oldpc != xc->regs.pc);
816#endif
817
818    assert(status() == Running ||
819           status() == Idle ||
820           status() == DcacheMissStall);
821
822    if (status() == Running && !tickEvent.scheduled())
823        tickEvent.schedule(curTick + cycles(1));
824}
825
826////////////////////////////////////////////////////////////////////////
827//
828//  SimpleCPU Simulation Object
829//
830BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
831
832    Param<Counter> max_insts_any_thread;
833    Param<Counter> max_insts_all_threads;
834    Param<Counter> max_loads_any_thread;
835    Param<Counter> max_loads_all_threads;
836
837#if FULL_SYSTEM
838    SimObjectParam<AlphaITB *> itb;
839    SimObjectParam<AlphaDTB *> dtb;
840    SimObjectParam<FunctionalMemory *> mem;
841    SimObjectParam<System *> system;
842    Param<int> cpu_id;
843    Param<Tick> profile;
844#else
845    SimObjectParam<Process *> workload;
846#endif // FULL_SYSTEM
847
848    Param<int> clock;
849    SimObjectParam<BaseMem *> icache;
850    SimObjectParam<BaseMem *> dcache;
851
852    Param<bool> defer_registration;
853    Param<int> width;
854    Param<bool> function_trace;
855    Param<Tick> function_trace_start;
856
857END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
858
859BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
860
861    INIT_PARAM(max_insts_any_thread,
862               "terminate when any thread reaches this inst count"),
863    INIT_PARAM(max_insts_all_threads,
864               "terminate when all threads have reached this inst count"),
865    INIT_PARAM(max_loads_any_thread,
866               "terminate when any thread reaches this load count"),
867    INIT_PARAM(max_loads_all_threads,
868               "terminate when all threads have reached this load count"),
869
870#if FULL_SYSTEM
871    INIT_PARAM(itb, "Instruction TLB"),
872    INIT_PARAM(dtb, "Data TLB"),
873    INIT_PARAM(mem, "memory"),
874    INIT_PARAM(system, "system object"),
875    INIT_PARAM(cpu_id, "processor ID"),
876    INIT_PARAM(profile, ""),
877#else
878    INIT_PARAM(workload, "processes to run"),
879#endif // FULL_SYSTEM
880
881    INIT_PARAM(clock, "clock speed"),
882    INIT_PARAM(icache, "L1 instruction cache object"),
883    INIT_PARAM(dcache, "L1 data cache object"),
884    INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
885    INIT_PARAM(width, "cpu width"),
886    INIT_PARAM(function_trace, "Enable function trace"),
887    INIT_PARAM(function_trace_start, "Cycle to start function trace")
888
889END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
890
891
892CREATE_SIM_OBJECT(SimpleCPU)
893{
894    SimpleCPU::Params *params = new SimpleCPU::Params();
895    params->name = getInstanceName();
896    params->numberOfThreads = 1;
897    params->max_insts_any_thread = max_insts_any_thread;
898    params->max_insts_all_threads = max_insts_all_threads;
899    params->max_loads_any_thread = max_loads_any_thread;
900    params->max_loads_all_threads = max_loads_all_threads;
901    params->deferRegistration = defer_registration;
902    params->clock = clock;
903    params->functionTrace = function_trace;
904    params->functionTraceStart = function_trace_start;
905    params->icache_interface = (icache) ? icache->getInterface() : NULL;
906    params->dcache_interface = (dcache) ? dcache->getInterface() : NULL;
907    params->width = width;
908
909#if FULL_SYSTEM
910    params->itb = itb;
911    params->dtb = dtb;
912    params->mem = mem;
913    params->system = system;
914    params->cpu_id = cpu_id;
915    params->profile = profile;
916#else
917    params->process = workload;
918#endif
919
920    SimpleCPU *cpu = new SimpleCPU(params);
921    return cpu;
922}
923
924REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
925
926