base.cc revision 2012
11689SN/A/* 22325SN/A * Copyright (c) 2002-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292756Sksewell@umich.edu#include <cmath> 301689SN/A#include <cstdio> 311689SN/A#include <cstdlib> 321858SN/A#include <iostream> 332733Sktlim@umich.edu#include <iomanip> 341858SN/A#include <list> 351858SN/A#include <sstream> 362356SN/A#include <string> 371060SN/A 381060SN/A#include "base/cprintf.hh" 391060SN/A#include "base/inifile.hh" 401060SN/A#include "base/loader/symtab.hh" 411060SN/A#include "base/misc.hh" 422325SN/A#include "base/pollevent.hh" 432683Sktlim@umich.edu#include "base/range.hh" 442680Sktlim@umich.edu#include "base/stats/events.hh" 452817Sksewell@umich.edu#include "base/trace.hh" 461717SN/A#include "cpu/base.hh" 471060SN/A#include "cpu/exec_context.hh" 482325SN/A#include "cpu/exetrace.hh" 492292SN/A#include "cpu/profile.hh" 502292SN/A#include "cpu/sampler/sampler.hh" 512794Sktlim@umich.edu#include "cpu/simple/cpu.hh" 522794Sktlim@umich.edu#include "cpu/smt.hh" 532794Sktlim@umich.edu#include "cpu/static_inst.hh" 542794Sktlim@umich.edu#include "kern/kernel_stats.hh" 551060SN/A#include "mem/base_mem.hh" 562669Sktlim@umich.edu#include "mem/mem_interface.hh" 571060SN/A#include "sim/builder.hh" 582733Sktlim@umich.edu#include "sim/debug.hh" 592292SN/A#include "sim/host.hh" 601060SN/A#include "sim/sim_events.hh" 611060SN/A#include "sim/sim_object.hh" 621060SN/A#include "sim/stats.hh" 632292SN/A 642733Sktlim@umich.edu#if FULL_SYSTEM 652292SN/A#include "base/remote_gdb.hh" 662292SN/A#include "mem/functional/memory_control.hh" 672292SN/A#include "mem/functional/physical.hh" 682292SN/A#include "sim/system.hh" 691060SN/A#include "targetarch/alpha_memory.hh" 701755SN/A#include "targetarch/stacktrace.hh" 711060SN/A#include "targetarch/vtophys.hh" 721060SN/A#else // !FULL_SYSTEM 731060SN/A#include "mem/functional/functional.hh" 741060SN/A#endif // FULL_SYSTEM 751060SN/A 761060SN/Ausing namespace std; 771755SN/A 781060SN/A 791060SN/ASimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w) 801060SN/A : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w) 811060SN/A{ 821060SN/A} 831060SN/A 841755SN/Avoid 851060SN/ASimpleCPU::TickEvent::process() 861755SN/A{ 871060SN/A int count = width; 881060SN/A do { 891060SN/A cpu->tick(); 902829Sksewell@umich.edu } while (--count > 0 && cpu->status() == Running); 913221Sktlim@umich.edu} 922829Sksewell@umich.edu 932829Sksewell@umich.educonst char * 942829Sksewell@umich.eduSimpleCPU::TickEvent::description() 952829Sksewell@umich.edu{ 962829Sksewell@umich.edu return "SimpleCPU tick event"; 972829Sksewell@umich.edu} 982829Sksewell@umich.edu 992829Sksewell@umich.edu 1002829Sksewell@umich.eduSimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu) 1012829Sksewell@umich.edu : Event(&mainEventQueue), cpu(_cpu) 1022829Sksewell@umich.edu{ 1032829Sksewell@umich.edu} 1042829Sksewell@umich.edu 1052829Sksewell@umich.eduvoid SimpleCPU::CacheCompletionEvent::process() 1062829Sksewell@umich.edu{ 1072829Sksewell@umich.edu cpu->processCacheCompletion(); 1082829Sksewell@umich.edu} 1092829Sksewell@umich.edu 1102829Sksewell@umich.educonst char * 1112829Sksewell@umich.eduSimpleCPU::CacheCompletionEvent::description() 1122829Sksewell@umich.edu{ 1132829Sksewell@umich.edu return "SimpleCPU cache completion event"; 1142829Sksewell@umich.edu} 1152829Sksewell@umich.edu 1162829Sksewell@umich.eduSimpleCPU::SimpleCPU(Params *p) 1172829Sksewell@umich.edu : BaseCPU(p), tickEvent(this, p->width), xc(NULL), 1182829Sksewell@umich.edu cacheCompletionEvent(this) 1192875Sksewell@umich.edu{ 1202875Sksewell@umich.edu _status = Idle; 1212875Sksewell@umich.edu#if FULL_SYSTEM 1222875Sksewell@umich.edu xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem); 1232875Sksewell@umich.edu 1242875Sksewell@umich.edu // initialize CPU, including PC 1252875Sksewell@umich.edu TheISA::initCPU(&xc->regs); 1262875Sksewell@umich.edu#else 1272875Sksewell@umich.edu xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0); 1282875Sksewell@umich.edu#endif // !FULL_SYSTEM 1292875Sksewell@umich.edu 1302875Sksewell@umich.edu icacheInterface = p->icache_interface; 1312875Sksewell@umich.edu dcacheInterface = p->dcache_interface; 1322875Sksewell@umich.edu 1332875Sksewell@umich.edu memReq = new MemReq(); 1342875Sksewell@umich.edu memReq->xc = xc; 1352875Sksewell@umich.edu memReq->asid = 0; 1362875Sksewell@umich.edu memReq->data = new uint8_t[64]; 1372875Sksewell@umich.edu 1383221Sktlim@umich.edu numInst = 0; 1393221Sktlim@umich.edu startNumInst = 0; 1402875Sksewell@umich.edu numLoad = 0; 1412875Sksewell@umich.edu startNumLoad = 0; 1422875Sksewell@umich.edu lastIcacheStall = 0; 1432875Sksewell@umich.edu lastDcacheStall = 0; 1442875Sksewell@umich.edu 1452875Sksewell@umich.edu execContexts.push_back(xc); 1462875Sksewell@umich.edu} 1472875Sksewell@umich.edu 1482875Sksewell@umich.eduSimpleCPU::~SimpleCPU() 1492875Sksewell@umich.edu{ 1502292SN/A} 1512733Sktlim@umich.edu 1521060SN/Avoid 1532292SN/ASimpleCPU::switchOut(Sampler *s) 1541060SN/A{ 1551060SN/A sampler = s; 1561060SN/A if (status() == DcacheMissStall) { 1571060SN/A DPRINTF(Sampler,"Outstanding dcache access, waiting for completion\n"); 1581060SN/A _status = DcacheMissSwitch; 1591060SN/A } 1602292SN/A else { 1611060SN/A _status = SwitchedOut; 1622831Sksewell@umich.edu 1632292SN/A if (tickEvent.scheduled()) 1642292SN/A tickEvent.squash(); 1651060SN/A 1662292SN/A sampler->signalSwitched(); 1672292SN/A } 1682292SN/A} 1691060SN/A 1702831Sksewell@umich.edu 1712292SN/Avoid 1722292SN/ASimpleCPU::takeOverFrom(BaseCPU *oldCPU) 1732292SN/A{ 1742292SN/A BaseCPU::takeOverFrom(oldCPU); 1751060SN/A 1762873Sktlim@umich.edu assert(!tickEvent.scheduled()); 1772873Sktlim@umich.edu 1782873Sktlim@umich.edu // if any of this CPU's ExecContexts are active, mark the CPU as 1792873Sktlim@umich.edu // running and schedule its tick event. 1802873Sktlim@umich.edu for (int i = 0; i < execContexts.size(); ++i) { 1812873Sktlim@umich.edu ExecContext *xc = execContexts[i]; 1822873Sktlim@umich.edu if (xc->status() == ExecContext::Active && _status != Running) { 1832873Sktlim@umich.edu _status = Running; 1841060SN/A tickEvent.schedule(curTick); 1851060SN/A } 1861858SN/A } 1872292SN/A} 1881060SN/A 1891060SN/A 1902843Sktlim@umich.eduvoid 1912316SN/ASimpleCPU::activateContext(int thread_num, int delay) 1922316SN/A{ 1931060SN/A assert(thread_num == 0); 1943221Sktlim@umich.edu assert(xc); 1953221Sktlim@umich.edu 1963221Sktlim@umich.edu assert(_status == Idle); 1973221Sktlim@umich.edu notIdleFraction++; 1983221Sktlim@umich.edu scheduleTickEvent(delay); 1991681SN/A _status = Running; 2002733Sktlim@umich.edu} 2012733Sktlim@umich.edu 2022794Sktlim@umich.edu 2032733Sktlim@umich.eduvoid 2042316SN/ASimpleCPU::suspendContext(int thread_num) 2052316SN/A{ 2062316SN/A assert(thread_num == 0); 2072316SN/A assert(xc); 2082316SN/A 2092794Sktlim@umich.edu assert(_status == Running); 2102794Sktlim@umich.edu notIdleFraction--; 2112794Sktlim@umich.edu unscheduleTickEvent(); 2122316SN/A _status = Idle; 2132316SN/A} 2141858SN/A 2152292SN/A 2162292SN/Avoid 2171681SN/ASimpleCPU::deallocateContext(int thread_num) 2181681SN/A{ 2192325SN/A // for now, these are equivalent 2202325SN/A suspendContext(thread_num); 2212325SN/A} 2221060SN/A 2232292SN/A 2242292SN/Avoid 2252292SN/ASimpleCPU::haltContext(int thread_num) 2262292SN/A{ 2272292SN/A // for now, these are equivalent 2282292SN/A suspendContext(thread_num); 2291060SN/A} 2301060SN/A 2311060SN/A 2321060SN/Avoid 2331060SN/ASimpleCPU::regStats() 2341060SN/A{ 2351060SN/A using namespace Stats; 2361060SN/A 2371060SN/A BaseCPU::regStats(); 2381060SN/A 2391060SN/A numInsts 2402292SN/A .name(name() + ".num_insts") 2411060SN/A .desc("Number of instructions executed") 2421060SN/A ; 2431060SN/A 2441060SN/A numMemRefs 2451060SN/A .name(name() + ".num_refs") 2461060SN/A .desc("Number of memory references") 2471060SN/A ; 2481060SN/A 2492292SN/A notIdleFraction 2502292SN/A .name(name() + ".not_idle_fraction") 2512292SN/A .desc("Percentage of non-idle cycles") 2522292SN/A ; 2532292SN/A 2542307SN/A idleFraction 2552831Sksewell@umich.edu .name(name() + ".idle_fraction") 2562831Sksewell@umich.edu .desc("Percentage of idle cycles") 2572831Sksewell@umich.edu ; 2582831Sksewell@umich.edu 2592831Sksewell@umich.edu icacheStallCycles 2602831Sksewell@umich.edu .name(name() + ".icache_stall_cycles") 2612292SN/A .desc("ICache total stall cycles") 2622307SN/A .prereq(icacheStallCycles) 2632292SN/A ; 2642292SN/A 2652316SN/A dcacheStallCycles 2662292SN/A .name(name() + ".dcache_stall_cycles") 2672292SN/A .desc("DCache total stall cycles") 2682292SN/A .prereq(dcacheStallCycles) 2692292SN/A ; 2702292SN/A 2712292SN/A idleFraction = constant(1.0) - notIdleFraction; 2721060SN/A} 2732292SN/A 2742292SN/Avoid 2751060SN/ASimpleCPU::resetStats() 2762292SN/A{ 2772307SN/A startNumInst = numInst; 2782292SN/A notIdleFraction = (_status != Idle); 2792292SN/A} 2802292SN/A 2812325SN/Avoid 2822292SN/ASimpleCPU::serialize(ostream &os) 2832292SN/A{ 2842292SN/A BaseCPU::serialize(os); 2852325SN/A SERIALIZE_ENUM(_status); 2862292SN/A SERIALIZE_SCALAR(inst); 2872292SN/A nameOut(os, csprintf("%s.xc", name())); 2882292SN/A xc->serialize(os); 2892292SN/A nameOut(os, csprintf("%s.tickEvent", name())); 2902292SN/A tickEvent.serialize(os); 2912292SN/A nameOut(os, csprintf("%s.cacheCompletionEvent", name())); 2922292SN/A cacheCompletionEvent.serialize(os); 2932292SN/A} 2942292SN/A 2952292SN/Avoid 2962292SN/ASimpleCPU::unserialize(Checkpoint *cp, const string §ion) 2972325SN/A{ 2982292SN/A BaseCPU::unserialize(cp, section); 2992292SN/A UNSERIALIZE_ENUM(_status); 3002292SN/A UNSERIALIZE_SCALAR(inst); 3012325SN/A xc->unserialize(cp, csprintf("%s.xc", section)); 3022292SN/A tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 3032292SN/A cacheCompletionEvent 3042292SN/A .unserialize(cp, csprintf("%s.cacheCompletionEvent", section)); 3052292SN/A} 3062292SN/A 3072292SN/Avoid 3082292SN/Achange_thread_state(int thread_number, int activate, int priority) 3092292SN/A{ 3103221Sktlim@umich.edu} 3113221Sktlim@umich.edu 3123221Sktlim@umich.eduFault 3132292SN/ASimpleCPU::copySrcTranslate(Addr src) 3142292SN/A{ 3152292SN/A static bool no_warn = true; 3162292SN/A int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 3172292SN/A // Only support block sizes of 64 atm. 3182292SN/A assert(blk_size == 64); 3192292SN/A int offset = src & (blk_size - 1); 3202292SN/A 3212292SN/A // Make sure block doesn't span page 3221060SN/A if (no_warn && 3232292SN/A (src & TheISA::PageMask) != ((src + blk_size) & TheISA::PageMask) && 3241060SN/A (src >> 40) != 0xfffffc) { 3251060SN/A warn("Copied block source spans pages %x.", src); 3262292SN/A no_warn = false; 3272292SN/A } 3282292SN/A 3292829Sksewell@umich.edu memReq->reset(src & ~(blk_size - 1), blk_size); 3302829Sksewell@umich.edu 3313093Sksewell@umich.edu // translate to physical address 3323093Sksewell@umich.edu Fault fault = xc->translateDataReadReq(memReq); 3333093Sksewell@umich.edu 3343093Sksewell@umich.edu assert(fault != Alignment_Fault); 3353093Sksewell@umich.edu 3362292SN/A if (fault == No_Fault) { 3371060SN/A xc->copySrcAddr = src; 3381060SN/A xc->copySrcPhysAddr = memReq->paddr + offset; 3391060SN/A } else { 3401755SN/A xc->copySrcAddr = 0; 3411060SN/A xc->copySrcPhysAddr = 0; 3421060SN/A } 3431060SN/A return fault; 3441060SN/A} 3451060SN/A 3461755SN/AFault 3471062SN/ASimpleCPU::copy(Addr dest) 3482733Sktlim@umich.edu{ 3492292SN/A static bool no_warn = true; 3502733Sktlim@umich.edu int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64; 3512292SN/A // Only support block sizes of 64 atm. 3522292SN/A assert(blk_size == 64); 3532292SN/A uint8_t data[blk_size]; 3542292SN/A //assert(xc->copySrcAddr); 3552292SN/A int offset = dest & (blk_size - 1); 3562292SN/A 3572292SN/A // Make sure block doesn't span page 3582292SN/A if (no_warn && 3592292SN/A (dest & TheISA::PageMask) != ((dest + blk_size) & TheISA::PageMask) && 3602292SN/A (dest >> 40) != 0xfffffc) { 3612292SN/A no_warn = false; 3622292SN/A warn("Copied block destination spans pages %x. ", dest); 3632292SN/A } 3642292SN/A 3652292SN/A memReq->reset(dest & ~(blk_size -1), blk_size); 3662292SN/A // translate to physical address 3672292SN/A Fault fault = xc->translateDataWriteReq(memReq); 3682292SN/A 3692292SN/A assert(fault != Alignment_Fault); 3702292SN/A 3712292SN/A if (fault == No_Fault) { 3722292SN/A Addr dest_addr = memReq->paddr + offset; 3732292SN/A // Need to read straight from memory since we have more than 8 bytes. 3742292SN/A memReq->paddr = xc->copySrcPhysAddr; 3752292SN/A xc->mem->read(memReq, data); 3762292SN/A memReq->paddr = dest_addr; 3772292SN/A xc->mem->write(memReq, data); 3782292SN/A if (dcacheInterface) { 3792292SN/A memReq->cmd = Copy; 3802292SN/A memReq->completionEvent = NULL; 3812292SN/A memReq->paddr = xc->copySrcPhysAddr; 3822292SN/A memReq->dest = dest_addr; 3832292SN/A memReq->size = 64; 3842292SN/A memReq->time = curTick; 3852292SN/A memReq->flags &= ~INST_READ; 3862292SN/A dcacheInterface->access(memReq); 3872292SN/A } 3882292SN/A } 3892292SN/A return fault; 3902292SN/A} 3912292SN/A 3922292SN/A// precise architected memory state accessor macros 3932292SN/Atemplate <class T> 3942292SN/AFault 3952292SN/ASimpleCPU::read(Addr addr, T &data, unsigned flags) 3962292SN/A{ 3972292SN/A if (status() == DcacheMissStall || status() == DcacheMissSwitch) { 3982292SN/A Fault fault = xc->read(memReq,data); 3992292SN/A 4001062SN/A if (traceData) { 4011062SN/A traceData->setAddr(addr); 4021062SN/A } 4032871Sktlim@umich.edu return fault; 4042871Sktlim@umich.edu } 4052871Sktlim@umich.edu 4062871Sktlim@umich.edu memReq->reset(addr, sizeof(T), flags); 4072871Sktlim@umich.edu 4082871Sktlim@umich.edu // translate to physical address 4092871Sktlim@umich.edu Fault fault = xc->translateDataReadReq(memReq); 4102871Sktlim@umich.edu 4112871Sktlim@umich.edu // if we have a cache, do cache access too 4122871Sktlim@umich.edu if (fault == No_Fault && dcacheInterface) { 4132871Sktlim@umich.edu memReq->cmd = Read; 4142871Sktlim@umich.edu memReq->completionEvent = NULL; 4151062SN/A memReq->time = curTick; 4161755SN/A memReq->flags &= ~INST_READ; 4171060SN/A MemAccessResult result = dcacheInterface->access(memReq); 4182733Sktlim@umich.edu 4191060SN/A // Ugly hack to get an event scheduled *only* if the access is 4202292SN/A // a miss. We really should add first-class support for this 4212292SN/A // at some point. 4222325SN/A if (result != MA_HIT && dcacheInterface->doEvents()) { 4232292SN/A memReq->completionEvent = &cacheCompletionEvent; 4242292SN/A lastDcacheStall = curTick; 4251060SN/A unscheduleTickEvent(); 4261060SN/A _status = DcacheMissStall; 4271060SN/A } else { 4281060SN/A // do functional access 4291060SN/A fault = xc->read(memReq, data); 4301060SN/A 4311060SN/A } 4321060SN/A } else if(fault == No_Fault) { 4331060SN/A // do functional access 4341060SN/A fault = xc->read(memReq, data); 4352292SN/A 4362292SN/A } 4372292SN/A 4382292SN/A if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 4392292SN/A recordEvent("Uncached Read"); 4401060SN/A 4411060SN/A return fault; 4421060SN/A} 4431060SN/A 4441060SN/A#ifndef DOXYGEN_SHOULD_SKIP_THIS 4451060SN/A 4461060SN/Atemplate 4472325SN/AFault 4482292SN/ASimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 4492292SN/A 4502292SN/Atemplate 4512292SN/AFault 4522292SN/ASimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 4532325SN/A 4542867Sktlim@umich.edutemplate 4552905Sktlim@umich.eduFault 4563226Sktlim@umich.eduSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags); 4572325SN/A 4582325SN/Atemplate 4593221Sktlim@umich.eduFault 4603226Sktlim@umich.eduSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags); 4612325SN/A 4622325SN/A#endif //DOXYGEN_SHOULD_SKIP_THIS 4632325SN/A 4642325SN/Atemplate<> 4653226Sktlim@umich.eduFault 4662325SN/ASimpleCPU::read(Addr addr, double &data, unsigned flags) 4672292SN/A{ 4682292SN/A return read(addr, *(uint64_t*)&data, flags); 4692292SN/A} 4702292SN/A 4712292SN/Atemplate<> 4722292SN/AFault 4731060SN/ASimpleCPU::read(Addr addr, float &data, unsigned flags) 4741060SN/A{ 4751060SN/A return read(addr, *(uint32_t*)&data, flags); 4761060SN/A} 4771755SN/A 4781060SN/A 4792307SN/Atemplate<> 4802680Sktlim@umich.eduFault 4812292SN/ASimpleCPU::read(Addr addr, int32_t &data, unsigned flags) 4821060SN/A{ 4832292SN/A return read(addr, (uint32_t&)data, flags); 4842292SN/A} 4852292SN/A 4862292SN/A 4872292SN/Atemplate <class T> 4882292SN/AFault 4891858SN/ASimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 4902680Sktlim@umich.edu{ 4911681SN/A memReq->reset(addr, sizeof(T), flags); 4922680Sktlim@umich.edu 4931681SN/A // translate to physical address 4942292SN/A Fault fault = xc->translateDataWriteReq(memReq); 4952680Sktlim@umich.edu 4962292SN/A // do functional access 4971060SN/A if (fault == No_Fault) 4981060SN/A fault = xc->write(memReq, data); 4992292SN/A 5002680Sktlim@umich.edu if (fault == No_Fault && dcacheInterface) { 5012292SN/A memReq->cmd = Write; 5022292SN/A memcpy(memReq->data,(uint8_t *)&data,memReq->size); 5032292SN/A memReq->completionEvent = NULL; 5042292SN/A memReq->time = curTick; 5052292SN/A memReq->flags &= ~INST_READ; 5062292SN/A MemAccessResult result = dcacheInterface->access(memReq); 5072292SN/A 5082316SN/A // Ugly hack to get an event scheduled *only* if the access is 5092292SN/A // a miss. We really should add first-class support for this 5102292SN/A // at some point. 5112292SN/A if (result != MA_HIT && dcacheInterface->doEvents()) { 5122292SN/A memReq->completionEvent = &cacheCompletionEvent; 5132292SN/A lastDcacheStall = curTick; 5142292SN/A unscheduleTickEvent(); 5152292SN/A _status = DcacheMissStall; 5162292SN/A } 5172292SN/A } 5182292SN/A 5192875Sksewell@umich.edu if (res && (fault == No_Fault)) 5202875Sksewell@umich.edu *res = memReq->result; 5212875Sksewell@umich.edu 5222875Sksewell@umich.edu if (!dcacheInterface && (memReq->flags & UNCACHEABLE)) 5232875Sksewell@umich.edu recordEvent("Uncached Write"); 5243226Sktlim@umich.edu 5253226Sktlim@umich.edu return fault; 5262875Sksewell@umich.edu} 5272875Sksewell@umich.edu 5282875Sksewell@umich.edu 5292875Sksewell@umich.edu#ifndef DOXYGEN_SHOULD_SKIP_THIS 5302875Sksewell@umich.edutemplate 5312875Sksewell@umich.eduFault 5322875Sksewell@umich.eduSimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res); 5332875Sksewell@umich.edu 5342875Sksewell@umich.edutemplate 5352875Sksewell@umich.eduFault 5362875Sksewell@umich.eduSimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res); 5372875Sksewell@umich.edu 5382875Sksewell@umich.edutemplate 5392875Sksewell@umich.eduFault 5402875Sksewell@umich.eduSimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res); 5412875Sksewell@umich.edu 5423226Sktlim@umich.edutemplate 5433226Sktlim@umich.eduFault 5442875Sksewell@umich.eduSimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res); 5452875Sksewell@umich.edu 5462875Sksewell@umich.edu#endif //DOXYGEN_SHOULD_SKIP_THIS 5472875Sksewell@umich.edu 5482875Sksewell@umich.edutemplate<> 5492875Sksewell@umich.eduFault 5502875Sksewell@umich.eduSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res) 5512875Sksewell@umich.edu{ 5522875Sksewell@umich.edu return write(*(uint64_t*)&data, addr, flags, res); 5532875Sksewell@umich.edu} 5542875Sksewell@umich.edu 5553686Sktlim@umich.edutemplate<> 5563686Sktlim@umich.eduFault 5573686Sktlim@umich.eduSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res) 5583686Sktlim@umich.edu{ 5593686Sktlim@umich.edu return write(*(uint32_t*)&data, addr, flags, res); 5603686Sktlim@umich.edu} 5612875Sksewell@umich.edu 5622875Sksewell@umich.edu 5632875Sksewell@umich.edutemplate<> 5642875Sksewell@umich.eduFault 5652875Sksewell@umich.eduSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res) 5662875Sksewell@umich.edu{ 5672875Sksewell@umich.edu return write((uint32_t)data, addr, flags, res); 5682875Sksewell@umich.edu} 5692875Sksewell@umich.edu 5703221Sktlim@umich.edu 5712875Sksewell@umich.edu#if FULL_SYSTEM 5722875Sksewell@umich.eduAddr 5732875Sksewell@umich.eduSimpleCPU::dbg_vtophys(Addr addr) 5742875Sksewell@umich.edu{ 5752875Sksewell@umich.edu return vtophys(xc, addr); 5762875Sksewell@umich.edu} 5772875Sksewell@umich.edu#endif // FULL_SYSTEM 5782875Sksewell@umich.edu 5792875Sksewell@umich.eduvoid 5802875Sksewell@umich.eduSimpleCPU::processCacheCompletion() 5812875Sksewell@umich.edu{ 5822875Sksewell@umich.edu switch (status()) { 5832875Sksewell@umich.edu case IcacheMissStall: 5842875Sksewell@umich.edu icacheStallCycles += curTick - lastIcacheStall; 5853221Sktlim@umich.edu _status = IcacheMissComplete; 5863221Sktlim@umich.edu scheduleTickEvent(1); 5872875Sksewell@umich.edu break; 5882875Sksewell@umich.edu case DcacheMissStall: 5892875Sksewell@umich.edu if (memReq->cmd.isRead()) { 5902875Sksewell@umich.edu curStaticInst->execute(this,traceData); 5912875Sksewell@umich.edu if (traceData) 5923221Sktlim@umich.edu traceData->finalize(); 5933221Sktlim@umich.edu } 5942875Sksewell@umich.edu dcacheStallCycles += curTick - lastDcacheStall; 5952875Sksewell@umich.edu _status = Running; 5963221Sktlim@umich.edu scheduleTickEvent(1); 5973221Sktlim@umich.edu break; 5983221Sktlim@umich.edu case DcacheMissSwitch: 5992875Sksewell@umich.edu if (memReq->cmd.isRead()) { 6002875Sksewell@umich.edu curStaticInst->execute(this,traceData); 6012875Sksewell@umich.edu if (traceData) 6022875Sksewell@umich.edu traceData->finalize(); 6032875Sksewell@umich.edu } 6042875Sksewell@umich.edu _status = SwitchedOut; 6052875Sksewell@umich.edu sampler->signalSwitched(); 6062875Sksewell@umich.edu case SwitchedOut: 6073221Sktlim@umich.edu // If this CPU has been switched out due to sampling/warm-up, 6083221Sktlim@umich.edu // ignore any further status changes (e.g., due to cache 6093221Sktlim@umich.edu // misses outstanding at the time of the switch). 6102910Sksewell@umich.edu return; 6112875Sksewell@umich.edu default: 6122875Sksewell@umich.edu panic("SimpleCPU::processCacheCompletion: bad state"); 6132875Sksewell@umich.edu break; 6142875Sksewell@umich.edu } 6152875Sksewell@umich.edu} 6162875Sksewell@umich.edu 6172875Sksewell@umich.edu#if FULL_SYSTEM 6182910Sksewell@umich.eduvoid 6192910Sksewell@umich.eduSimpleCPU::post_interrupt(int int_num, int index) 6203221Sktlim@umich.edu{ 6212875Sksewell@umich.edu BaseCPU::post_interrupt(int_num, index); 6222875Sksewell@umich.edu 6232875Sksewell@umich.edu if (xc->status() == ExecContext::Suspended) { 6242875Sksewell@umich.edu DPRINTF(IPI,"Suspended Processor awoke\n"); 6252292SN/A xc->activate(); 6262292SN/A } 6272847Sksewell@umich.edu} 6282292SN/A#endif // FULL_SYSTEM 6292683Sktlim@umich.edu 6302292SN/A/* start simulation, program loaded, processor precise state initialized */ 6312680Sktlim@umich.eduvoid 6322292SN/ASimpleCPU::tick() 6332847Sksewell@umich.edu{ 6342292SN/A numCycles++; 6352292SN/A 6362292SN/A traceData = NULL; 6372292SN/A 6382292SN/A Fault fault = No_Fault; 6392292SN/A 6402292SN/A#if FULL_SYSTEM 6412292SN/A if (checkInterrupts && check_interrupts() && !xc->inPalMode() && 6422292SN/A status() != IcacheMissComplete) { 6432292SN/A int ipl = 0; 6442292SN/A int summary = 0; 6452292SN/A checkInterrupts = false; 6462292SN/A IntReg *ipr = xc->regs.ipr; 6472292SN/A 6482292SN/A if (xc->regs.ipr[TheISA::IPR_SIRR]) { 6492292SN/A for (int i = TheISA::INTLEVEL_SOFTWARE_MIN; 6502292SN/A i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) { 6512292SN/A if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) { 6522292SN/A // See table 4-19 of 21164 hardware reference 6532847Sksewell@umich.edu ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1; 6542292SN/A summary |= (ULL(1) << i); 6552847Sksewell@umich.edu } 6562847Sksewell@umich.edu } 6572847Sksewell@umich.edu } 6583093Sksewell@umich.edu 6592847Sksewell@umich.edu uint64_t interrupts = xc->cpu->intr_status(); 6602847Sksewell@umich.edu for (int i = TheISA::INTLEVEL_EXTERNAL_MIN; 6612292SN/A i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) { 6622680Sktlim@umich.edu if (interrupts & (ULL(1) << i)) { 6632292SN/A // See table 4-19 of 21164 hardware reference 6642292SN/A ipl = i; 6652292SN/A summary |= (ULL(1) << i); 6662292SN/A } 6672292SN/A } 6682292SN/A 6692292SN/A if (ipr[TheISA::IPR_ASTRR]) 6702292SN/A panic("asynchronous traps not implemented\n"); 6712292SN/A 6722292SN/A if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) { 6732292SN/A ipr[TheISA::IPR_ISR] = summary; 6742292SN/A ipr[TheISA::IPR_INTID] = ipl; 6752877Sksewell@umich.edu xc->ev5_trap(Interrupt_Fault); 6762847Sksewell@umich.edu 6772847Sksewell@umich.edu DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", 6782847Sksewell@umich.edu ipr[TheISA::IPR_IPLR], ipl, summary); 6792847Sksewell@umich.edu } 6802847Sksewell@umich.edu } 6812847Sksewell@umich.edu#endif 6822292SN/A 6832292SN/A // maintain $r0 semantics 6842292SN/A xc->regs.intRegFile[ZeroReg] = 0; 6852292SN/A#ifdef TARGET_ALPHA 6862292SN/A xc->regs.floatRegFile.d[ZeroReg] = 0.0; 6872292SN/A#endif // TARGET_ALPHA 6882292SN/A 6892847Sksewell@umich.edu if (status() == IcacheMissComplete) { 6902292SN/A // We've already fetched an instruction and were stalled on an 6912292SN/A // I-cache miss. No need to fetch it again. 6922292SN/A 6932292SN/A // Set status to running; tick event will get rescheduled if 6942292SN/A // necessary at end of tick() function. 6952292SN/A _status = Running; 6962292SN/A } 6972847Sksewell@umich.edu else { 6982935Sksewell@umich.edu // Try to fetch an instruction 6992935Sksewell@umich.edu 7002292SN/A // set up memory request for instruction fetch 7012935Sksewell@umich.edu#if FULL_SYSTEM 7022875Sksewell@umich.edu#define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0 7032935Sksewell@umich.edu#else 7042292SN/A#define IFETCH_FLAGS(pc) 0 7052292SN/A#endif 7062292SN/A 7072847Sksewell@umich.edu memReq->cmd = Read; 7083229Sktlim@umich.edu memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t), 7093229Sktlim@umich.edu IFETCH_FLAGS(xc->regs.pc)); 7103229Sktlim@umich.edu 7113229Sktlim@umich.edu fault = xc->translateInstReq(memReq); 7123229Sktlim@umich.edu 7133229Sktlim@umich.edu if (fault == No_Fault) 7142292SN/A fault = xc->mem->read(memReq, inst); 7152292SN/A 7162292SN/A if (icacheInterface && fault == No_Fault) { 7172292SN/A memReq->completionEvent = NULL; 7183229Sktlim@umich.edu 7192292SN/A memReq->time = curTick; 7202292SN/A memReq->flags |= INST_READ; 7212292SN/A MemAccessResult result = icacheInterface->access(memReq); 7222292SN/A 7232292SN/A // Ugly hack to get an event scheduled *only* if the access is 7242292SN/A // a miss. We really should add first-class support for this 7252292SN/A // at some point. 7262733Sktlim@umich.edu if (result != MA_HIT && icacheInterface->doEvents()) { 7272292SN/A memReq->completionEvent = &cacheCompletionEvent; 7282292SN/A lastIcacheStall = curTick; 7292292SN/A unscheduleTickEvent(); 7302292SN/A _status = IcacheMissStall; 7312292SN/A return; 7322292SN/A } 7332733Sktlim@umich.edu } 7342292SN/A } 7352292SN/A 7362292SN/A // If we've got a valid instruction (i.e., no fault on instruction 7372292SN/A // fetch), then execute it. 7382733Sktlim@umich.edu if (fault == No_Fault) { 7392292SN/A 7402292SN/A // keep an instruction count 7412292SN/A numInst++; 7422292SN/A numInsts++; 7432292SN/A 7442733Sktlim@umich.edu // check for instruction-count-based events 7452292SN/A comInstEventQueue[0]->serviceEvents(numInst); 7462292SN/A 7472292SN/A // decode the instruction 7482292SN/A inst = gtoh(inst); 7492292SN/A curStaticInst = StaticInst<TheISA>::decode(inst); 7502733Sktlim@umich.edu 7512292SN/A traceData = Trace::getInstRecord(curTick, xc, this, curStaticInst, 7522292SN/A xc->regs.pc); 7532292SN/A 7542292SN/A#if FULL_SYSTEM 7552292SN/A xc->setInst(inst); 7562733Sktlim@umich.edu#endif // FULL_SYSTEM 7572292SN/A 7582292SN/A xc->func_exe_inst++; 7592292SN/A 7602292SN/A fault = curStaticInst->execute(this, traceData); 7612292SN/A 7622292SN/A#if FULL_SYSTEM 7632292SN/A if (xc->fnbin) { 7642292SN/A assert(xc->kernelStats); 7652292SN/A system->kernelBinning->execute(xc, inst); 7662292SN/A } 7672292SN/A 7682292SN/A if (xc->profile) { 7692292SN/A bool usermode = (xc->regs.ipr[AlphaISA::IPR_DTB_CM] & 0x18) != 0; 7702292SN/A xc->profilePC = usermode ? 1 : xc->regs.pc; 7712292SN/A ProfileNode *node = xc->profile->consume(xc, inst); 7722292SN/A if (node) 7732292SN/A xc->profileNode = node; 7742875Sksewell@umich.edu } 7752292SN/A#endif 7762292SN/A 7771060SN/A if (curStaticInst->isMemRef()) { 7781060SN/A numMemRefs++; 7791060SN/A } 7801060SN/A 7812852Sktlim@umich.edu if (curStaticInst->isLoad()) { 7822864Sktlim@umich.edu ++numLoad; 7832864Sktlim@umich.edu comLoadEventQueue[0]->serviceEvents(numLoad); 7842918Sktlim@umich.edu } 7852918Sktlim@umich.edu 7862864Sktlim@umich.edu // If we have a dcache miss, then we can't finialize the instruction 7872864Sktlim@umich.edu // trace yet because we want to populate it with the data later 7882864Sktlim@umich.edu if (traceData && 7892864Sktlim@umich.edu !(status() == DcacheMissStall && memReq->cmd.isRead())) { 7902864Sktlim@umich.edu traceData->finalize(); 7912864Sktlim@umich.edu } 7922864Sktlim@umich.edu 7932864Sktlim@umich.edu traceFunctions(xc->regs.pc); 7942864Sktlim@umich.edu 7952864Sktlim@umich.edu } // if (fault == No_Fault) 7962864Sktlim@umich.edu 7972864Sktlim@umich.edu if (fault != No_Fault) { 7982864Sktlim@umich.edu#if FULL_SYSTEM 7992864Sktlim@umich.edu xc->ev5_trap(fault); 8002864Sktlim@umich.edu#else // !FULL_SYSTEM 8012864Sktlim@umich.edu fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc); 8022864Sktlim@umich.edu#endif // FULL_SYSTEM 8032864Sktlim@umich.edu } 8042864Sktlim@umich.edu else { 8052864Sktlim@umich.edu // go to the next instruction 8062918Sktlim@umich.edu xc->regs.pc = xc->regs.npc; 8072918Sktlim@umich.edu xc->regs.npc += sizeof(MachInst); 8082864Sktlim@umich.edu } 8092864Sktlim@umich.edu 8102864Sktlim@umich.edu#if FULL_SYSTEM 8112864Sktlim@umich.edu Addr oldpc; 8122864Sktlim@umich.edu do { 8132864Sktlim@umich.edu oldpc = xc->regs.pc; 8142864Sktlim@umich.edu system->pcEventQueue.service(xc); 8152864Sktlim@umich.edu } while (oldpc != xc->regs.pc); 8162864Sktlim@umich.edu#endif 8172864Sktlim@umich.edu 8182864Sktlim@umich.edu assert(status() == Running || 8192864Sktlim@umich.edu status() == Idle || 8202864Sktlim@umich.edu status() == DcacheMissStall); 8212864Sktlim@umich.edu 8222864Sktlim@umich.edu if (status() == Running && !tickEvent.scheduled()) 8232864Sktlim@umich.edu tickEvent.schedule(curTick + cycles(1)); 8242905Sktlim@umich.edu} 8252843Sktlim@umich.edu 8261060SN/A//////////////////////////////////////////////////////////////////////// 8273125Sktlim@umich.edu// 8283512Sktlim@umich.edu// SimpleCPU Simulation Object 8293512Sktlim@umich.edu// 8303512Sktlim@umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 8313512Sktlim@umich.edu 8323512Sktlim@umich.edu Param<Counter> max_insts_any_thread; 8333512Sktlim@umich.edu Param<Counter> max_insts_all_threads; 8342843Sktlim@umich.edu Param<Counter> max_loads_any_thread; 8352843Sktlim@umich.edu Param<Counter> max_loads_all_threads; 8362843Sktlim@umich.edu 8372843Sktlim@umich.edu#if FULL_SYSTEM 8382843Sktlim@umich.edu SimObjectParam<AlphaITB *> itb; 8392843Sktlim@umich.edu SimObjectParam<AlphaDTB *> dtb; 8402325SN/A SimObjectParam<FunctionalMemory *> mem; 8412325SN/A SimObjectParam<System *> system; 8422863Sktlim@umich.edu Param<int> cpu_id; 8432905Sktlim@umich.edu Param<Tick> profile; 8442864Sktlim@umich.edu#else 8452864Sktlim@umich.edu SimObjectParam<Process *> workload; 8462864Sktlim@umich.edu#endif // FULL_SYSTEM 8472864Sktlim@umich.edu 8482864Sktlim@umich.edu Param<int> clock; 8492843Sktlim@umich.edu SimObjectParam<BaseMem *> icache; 8502863Sktlim@umich.edu SimObjectParam<BaseMem *> dcache; 8512863Sktlim@umich.edu 8522852Sktlim@umich.edu Param<bool> defer_registration; 8532905Sktlim@umich.edu Param<int> width; 8542863Sktlim@umich.edu Param<bool> function_trace; 8552905Sktlim@umich.edu Param<Tick> function_trace_start; 8562863Sktlim@umich.edu 8572316SN/AEND_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) 8582310SN/A 8592316SN/ABEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 8602316SN/A 8612843Sktlim@umich.edu INIT_PARAM(max_insts_any_thread, 8622316SN/A "terminate when any thread reaches this inst count"), 8632843Sktlim@umich.edu INIT_PARAM(max_insts_all_threads, 8642843Sktlim@umich.edu "terminate when all threads have reached this inst count"), 8652843Sktlim@umich.edu INIT_PARAM(max_loads_any_thread, 8662843Sktlim@umich.edu "terminate when any thread reaches this load count"), 8672843Sktlim@umich.edu INIT_PARAM(max_loads_all_threads, 8682316SN/A "terminate when all threads have reached this load count"), 8692905Sktlim@umich.edu 8702905Sktlim@umich.edu#if FULL_SYSTEM 8712864Sktlim@umich.edu INIT_PARAM(itb, "Instruction TLB"), 8722864Sktlim@umich.edu INIT_PARAM(dtb, "Data TLB"), 8732864Sktlim@umich.edu INIT_PARAM(mem, "memory"), 8743319Shsul@eecs.umich.edu INIT_PARAM(system, "system object"), 8753319Shsul@eecs.umich.edu INIT_PARAM(cpu_id, "processor ID"), 8763319Shsul@eecs.umich.edu INIT_PARAM(profile, ""), 8773319Shsul@eecs.umich.edu#else 8782843Sktlim@umich.edu INIT_PARAM(workload, "processes to run"), 8792843Sktlim@umich.edu#endif // FULL_SYSTEM 8802843Sktlim@umich.edu 8812843Sktlim@umich.edu INIT_PARAM(clock, "clock speed"), 8822316SN/A INIT_PARAM(icache, "L1 instruction cache object"), 8832843Sktlim@umich.edu INIT_PARAM(dcache, "L1 data cache object"), 8842843Sktlim@umich.edu INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 8852843Sktlim@umich.edu INIT_PARAM(width, "cpu width"), 8862843Sktlim@umich.edu INIT_PARAM(function_trace, "Enable function trace"), 8872843Sktlim@umich.edu INIT_PARAM(function_trace_start, "Cycle to start function trace") 8882316SN/A 8892316SN/AEND_INIT_SIM_OBJECT_PARAMS(SimpleCPU) 8902863Sktlim@umich.edu 8912905Sktlim@umich.edu 8922863Sktlim@umich.eduCREATE_SIM_OBJECT(SimpleCPU) 8933126Sktlim@umich.edu{ 8943126Sktlim@umich.edu SimpleCPU::Params *params = new SimpleCPU::Params(); 8952863Sktlim@umich.edu params->name = getInstanceName(); 8962863Sktlim@umich.edu params->numberOfThreads = 1; 8972863Sktlim@umich.edu params->max_insts_any_thread = max_insts_any_thread; 8982863Sktlim@umich.edu params->max_insts_all_threads = max_insts_all_threads; 8992310SN/A params->max_loads_any_thread = max_loads_any_thread; 9002843Sktlim@umich.edu params->max_loads_all_threads = max_loads_all_threads; 9012843Sktlim@umich.edu params->deferRegistration = defer_registration; 9022843Sktlim@umich.edu params->clock = clock; 9032843Sktlim@umich.edu params->functionTrace = function_trace; 9042843Sktlim@umich.edu params->functionTraceStart = function_trace_start; 9052843Sktlim@umich.edu params->icache_interface = (icache) ? icache->getInterface() : NULL; 9062843Sktlim@umich.edu params->dcache_interface = (dcache) ? dcache->getInterface() : NULL; 9072843Sktlim@umich.edu params->width = width; 9082843Sktlim@umich.edu 9092325SN/A#if FULL_SYSTEM 9102843Sktlim@umich.edu params->itb = itb; 9112843Sktlim@umich.edu params->dtb = dtb; 9122843Sktlim@umich.edu params->mem = mem; 9132843Sktlim@umich.edu params->system = system; 9142843Sktlim@umich.edu params->cpu_id = cpu_id; 9152843Sktlim@umich.edu params->profile = profile; 9162843Sktlim@umich.edu#else 9172843Sktlim@umich.edu params->process = workload; 9182843Sktlim@umich.edu#endif 9192843Sktlim@umich.edu 9202843Sktlim@umich.edu SimpleCPU *cpu = new SimpleCPU(params); 9213126Sktlim@umich.edu return cpu; 9223126Sktlim@umich.edu} 9231060SN/A 9241060SN/AREGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU) 9251060SN/A 9261060SN/A