comm.hh revision 1062
18504SN/A#ifndef __COMM_HH__ 28504SN/A#define __COMM_HH__ 38504SN/A 49988Snilay@cs.wisc.edu#include <stdint.h> 58825Snilay@cs.wisc.edu#include <vector> 69988Snilay@cs.wisc.edu#include "arch/alpha/isa_traits.hh" 78504SN/A#include "cpu/inst_seq.hh" 88504SN/A 98504SN/Ausing namespace std; 108504SN/A 118504SN/A// Find better place to put this typedef. 128504SN/A// The impl might be the best place for this. 1310315Snilay@cs.wisc.edutypedef short int PhysRegIndex; 148504SN/A 158504SN/Atemplate<class Impl> 169885Sstever@gmail.comstruct SimpleFetchSimpleDecode { 179885Sstever@gmail.com typedef typename Impl::DynInstPtr DynInstPtr; 188504SN/A 199988Snilay@cs.wisc.edu int size; 208504SN/A 218504SN/A DynInstPtr insts[Impl::MaxWidth + 1]; 228504SN/A}; 2311245Sandreas.sandberg@arm.com 2410315Snilay@cs.wisc.edutemplate<class Impl> 258504SN/Astruct SimpleDecodeSimpleRename { 2610242Ssteve.reinhardt@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 278504SN/A 289449SAli.Saidi@ARM.com int size; 298504SN/A 3010791Ssteve.reinhardt@amd.com DynInstPtr insts[Impl::MaxWidth + 1]; 3111245Sandreas.sandberg@arm.com}; 328673SN/A 3311245Sandreas.sandberg@arm.comtemplate<class Impl> 348504SN/Astruct SimpleRenameSimpleIEW { 358504SN/A typedef typename Impl::DynInstPtr DynInstPtr; 368504SN/A 378504SN/A int size; 388504SN/A 398504SN/A DynInstPtr insts[Impl::MaxWidth + 1]; 408504SN/A}; 418504SN/A 428504SN/Atemplate<class Impl> 438963Sgblack@eecs.umich.edustruct SimpleIEWSimpleCommit { 448504SN/A typedef typename Impl::DynInstPtr DynInstPtr; 458504SN/A 468504SN/A int size; 478504SN/A 489988Snilay@cs.wisc.edu DynInstPtr insts[Impl::MaxWidth + 1]; 498504SN/A 508504SN/A bool squash; 518504SN/A bool branchMispredict; 528504SN/A bool branchTaken; 538504SN/A uint64_t mispredPC; 548504SN/A uint64_t nextPC; 558504SN/A unsigned globalHist; 568504SN/A InstSeqNum squashedSeqNum; 578504SN/A}; 588504SN/A 599988Snilay@cs.wisc.edutemplate<class Impl> 608504SN/Astruct IssueStruct { 618504SN/A typedef typename Impl::DynInstPtr DynInstPtr; 628504SN/A 638504SN/A int size; 648835SAli.Saidi@ARM.com 658835SAli.Saidi@ARM.com DynInstPtr insts[Impl::MaxWidth + 1]; 669885Sstever@gmail.com}; 678835SAli.Saidi@ARM.com 689988Snilay@cs.wisc.edustruct TimeBufStruct { 698835SAli.Saidi@ARM.com struct decodeComm { 708835SAli.Saidi@ARM.com bool squash; 718835SAli.Saidi@ARM.com bool stall; 728963Sgblack@eecs.umich.edu bool predIncorrect; 738963Sgblack@eecs.umich.edu uint64_t branchAddr; 748835SAli.Saidi@ARM.com 758504SN/A InstSeqNum doneSeqNum; 768504SN/A 779885Sstever@gmail.com // Might want to package this kind of branch stuff into a single 788504SN/A // struct as it is used pretty frequently. 799988Snilay@cs.wisc.edu bool branchMispredict; 8010451Snilay@cs.wisc.edu bool branchTaken; 818721SN/A uint64_t mispredPC; 828721SN/A uint64_t nextPC; 838963Sgblack@eecs.umich.edu unsigned globalHist; 849885Sstever@gmail.com }; 859885Sstever@gmail.com 869885Sstever@gmail.com decodeComm decodeInfo; 879885Sstever@gmail.com 889885Sstever@gmail.com // Rename can't actually tell anything to squash or send a new PC back 8910315Snilay@cs.wisc.edu // because it doesn't do anything along those lines. But maybe leave 909988Snilay@cs.wisc.edu // these fields in here to keep the stages mostly orthagonal. 9110315Snilay@cs.wisc.edu struct renameComm { 929885Sstever@gmail.com bool squash; 938504SN/A bool stall; 948504SN/A 958504SN/A uint64_t nextPC; 969885Sstever@gmail.com }; 978504SN/A 988504SN/A renameComm renameInfo; 998504SN/A 1008504SN/A struct iewComm { 1018504SN/A bool stall; 1028504SN/A 1038504SN/A // Also eventually include skid buffer space. 1048504SN/A unsigned freeIQEntries; 1059481Snilay@cs.wisc.edu }; 1068504SN/A 1078504SN/A iewComm iewInfo; 1089885Sstever@gmail.com 1098504SN/A struct commitComm { 1108504SN/A bool squash; 1118504SN/A bool stall; 1128504SN/A unsigned freeROBEntries; 1138504SN/A 1148504SN/A bool branchMispredict; 1158504SN/A bool branchTaken; 1168504SN/A uint64_t mispredPC; 1178504SN/A uint64_t nextPC; 1188504SN/A unsigned globalHist; 1198504SN/A 1208504SN/A // Think of better names here. 1218504SN/A // Will need to be a variety of sizes... 1228504SN/A // Maybe make it a vector, that way only need one object. 1239988Snilay@cs.wisc.edu std::vector<PhysRegIndex> freeRegs; 1249988Snilay@cs.wisc.edu 12510451Snilay@cs.wisc.edu bool robSquashing; 1268504SN/A 1278504SN/A // Represents the instruction that has either been retired or 1288504SN/A // squashed. Similar to having a single bus that broadcasts the 1298504SN/A // retired or squashed sequence number. 1308504SN/A InstSeqNum doneSeqNum; 1318504SN/A 1328504SN/A // Extra bits of information so that the LDSTQ only updates when it 1338504SN/A // needs to. 1348504SN/A bool commitIsStore; 1358504SN/A bool commitIsLoad; 1368504SN/A 1378504SN/A // Communication specifically to the IQ to tell the IQ that it can 1389348SAli.Saidi@ARM.com // schedule a non-speculative instruction. 1398504SN/A InstSeqNum nonSpecSeqNum; 1408504SN/A }; 1418504SN/A 1428504SN/A commitComm commitInfo; 1438504SN/A}; 1448504SN/A 1458504SN/A#endif //__COMM_HH__ 1468728SN/A