comm.hh revision 1062 
1#ifndef __COMM_HH__
2#define __COMM_HH__
3
4#include <stdint.h>
5#include <vector>
6#include "arch/alpha/isa_traits.hh"
7#include "cpu/inst_seq.hh"
8
9using namespace std;
10
11// Find better place to put this typedef.
12// The impl might be the best place for this.
13typedef short int PhysRegIndex;
14
15template<class Impl>
16struct SimpleFetchSimpleDecode {
17    typedef typename Impl::DynInstPtr DynInstPtr;
18
19    int size;
20
21    DynInstPtr insts[Impl::MaxWidth + 1];
22};
23
24template<class Impl>
25struct SimpleDecodeSimpleRename {
26    typedef typename Impl::DynInstPtr DynInstPtr;
27
28    int size;
29
30    DynInstPtr insts[Impl::MaxWidth + 1];
31};
32
33template<class Impl>
34struct SimpleRenameSimpleIEW {
35    typedef typename Impl::DynInstPtr DynInstPtr;
36
37    int size;
38
39    DynInstPtr insts[Impl::MaxWidth + 1];
40};
41
42template<class Impl>
43struct SimpleIEWSimpleCommit {
44    typedef typename Impl::DynInstPtr DynInstPtr;
45
46    int size;
47
48    DynInstPtr insts[Impl::MaxWidth + 1];
49
50    bool squash;
51    bool branchMispredict;
52    bool branchTaken;
53    uint64_t mispredPC;
54    uint64_t nextPC;
55    unsigned globalHist;
56    InstSeqNum squashedSeqNum;
57};
58
59template<class Impl>
60struct IssueStruct {
61    typedef typename Impl::DynInstPtr DynInstPtr;
62
63    int size;
64
65    DynInstPtr insts[Impl::MaxWidth + 1];
66};
67
68struct TimeBufStruct {
69    struct decodeComm {
70        bool squash;
71        bool stall;
72        bool predIncorrect;
73        uint64_t branchAddr;
74
75        InstSeqNum doneSeqNum;
76
77        // Might want to package this kind of branch stuff into a single
78        // struct as it is used pretty frequently.
79        bool branchMispredict;
80        bool branchTaken;
81        uint64_t mispredPC;
82        uint64_t nextPC;
83        unsigned globalHist;
84    };
85
86    decodeComm decodeInfo;
87
88    // Rename can't actually tell anything to squash or send a new PC back
89    // because it doesn't do anything along those lines.  But maybe leave
90    // these fields in here to keep the stages mostly orthagonal.
91    struct renameComm {
92        bool squash;
93        bool stall;
94
95        uint64_t nextPC;
96    };
97
98    renameComm renameInfo;
99
100    struct iewComm {
101        bool stall;
102
103        // Also eventually include skid buffer space.
104        unsigned freeIQEntries;
105    };
106
107    iewComm iewInfo;
108
109    struct commitComm {
110        bool squash;
111        bool stall;
112        unsigned freeROBEntries;
113
114        bool branchMispredict;
115        bool branchTaken;
116        uint64_t mispredPC;
117        uint64_t nextPC;
118        unsigned globalHist;
119
120        // Think of better names here.
121        // Will need to be a variety of sizes...
122        // Maybe make it a vector, that way only need one object.
123        std::vector<PhysRegIndex> freeRegs;
124
125        bool robSquashing;
126
127        // Represents the instruction that has either been retired or
128        // squashed.  Similar to having a single bus that broadcasts the
129        // retired or squashed sequence number.
130        InstSeqNum doneSeqNum;
131
132        // Extra bits of information so that the LDSTQ only updates when it
133        // needs to.
134        bool commitIsStore;
135        bool commitIsLoad;
136
137        // Communication specifically to the IQ to tell the IQ that it can
138        // schedule a non-speculative instruction.
139        InstSeqNum nonSpecSeqNum;
140    };
141
142    commitComm commitInfo;
143};
144
145#endif //__COMM_HH__
146