registers.hh revision 9046
14120SN/A/* 24120SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company 34120SN/A * All rights reserved. 44120SN/A * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 134120SN/A * 147087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 157087Snate@binkert.org * modification, are permitted provided that the following conditions are 167087Snate@binkert.org * met: redistributions of source code must retain the above copyright 177087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 187087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 197087Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 207087Snate@binkert.org * documentation and/or other materials provided with the distribution; 217087Snate@binkert.org * neither the name of the copyright holders nor the names of its 224120SN/A * contributors may be used to endorse or promote products derived from 237087Snate@binkert.org * this software without specific prior written permission. 244120SN/A * 254120SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264120SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274120SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284120SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294120SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304120SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314120SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324120SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334120SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344120SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354120SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364120SN/A * 374120SN/A * Authors: Gabe Black 384120SN/A */ 394120SN/A 406329Sgblack@eecs.umich.edu#ifndef __ARCH_X86_REGISTERS_HH__ 416329Sgblack@eecs.umich.edu#define __ARCH_X86_REGISTERS_HH__ 426216SN/A 438961Sgblack@eecs.umich.edu#include "arch/x86/generated/max_inst_regs.hh" 447629Sgblack@eecs.umich.edu#include "arch/x86/regs/int.hh" 457629Sgblack@eecs.umich.edu#include "arch/x86/regs/misc.hh" 466315SN/A#include "arch/x86/x86_traits.hh" 474137SN/A 484120SN/Anamespace X86ISA 494120SN/A{ 506329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstSrcRegs; 516329Sgblack@eecs.umich.eduusing X86ISAInst::MaxInstDestRegs; 529046SAli.Saidi@ARM.comusing X86ISAInst::MaxMiscDestRegs; 536329Sgblack@eecs.umich.educonst int NumMiscArchRegs = NUM_MISCREGS; 546329Sgblack@eecs.umich.educonst int NumMiscRegs = NUM_MISCREGS; 556313SN/A 566329Sgblack@eecs.umich.educonst int NumIntArchRegs = NUM_INTREGS; 576329Sgblack@eecs.umich.educonst int NumIntRegs = 586329Sgblack@eecs.umich.edu NumIntArchRegs + NumMicroIntRegs + 596329Sgblack@eecs.umich.edu NumPseudoIntRegs + NumImplicitIntRegs; 606319SN/A 616329Sgblack@eecs.umich.edu//Each 128 bit xmm register is broken into two effective 64 bit registers. 626329Sgblack@eecs.umich.educonst int NumFloatRegs = 636329Sgblack@eecs.umich.edu NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; 646329Sgblack@eecs.umich.educonst int NumFloatArchRegs = NumFloatRegs + 8; 656315SN/A 666329Sgblack@eecs.umich.edu// These enumerate all the registers for dependence tracking. 676329Sgblack@eecs.umich.eduenum DependenceTags { 686329Sgblack@eecs.umich.edu //There are 16 microcode registers at the moment. This is an 696329Sgblack@eecs.umich.edu //unusually large constant to make sure there isn't overflow. 706329Sgblack@eecs.umich.edu FP_Base_DepTag = 128, 716329Sgblack@eecs.umich.edu Ctrl_Base_DepTag = 726329Sgblack@eecs.umich.edu FP_Base_DepTag + 736329Sgblack@eecs.umich.edu //mmx/x87 registers 746329Sgblack@eecs.umich.edu 8 + 756329Sgblack@eecs.umich.edu //xmm registers 766329Sgblack@eecs.umich.edu 16 * 2 + 776329Sgblack@eecs.umich.edu //The microcode fp registers 786329Sgblack@eecs.umich.edu 8 + 796329Sgblack@eecs.umich.edu //The indices that are mapped over the fp stack 807649Sminkyu.jeong@arm.com 8, 817649Sminkyu.jeong@arm.com Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs 826329Sgblack@eecs.umich.edu}; 834137SN/A 846329Sgblack@eecs.umich.edu// semantically meaningful register indices 856329Sgblack@eecs.umich.edu//There is no such register in X86 866329Sgblack@eecs.umich.educonst int ZeroReg = NUM_INTREGS; 876329Sgblack@eecs.umich.educonst int StackPointerReg = INTREG_RSP; 886329Sgblack@eecs.umich.edu//X86 doesn't seem to have a link register 896329Sgblack@eecs.umich.educonst int ReturnAddressReg = 0; 906329Sgblack@eecs.umich.educonst int ReturnValueReg = INTREG_RAX; 916329Sgblack@eecs.umich.educonst int FramePointerReg = INTREG_RBP; 924137SN/A 936329Sgblack@eecs.umich.edu// Some OS syscalls use a second register (rdx) to return a second 946329Sgblack@eecs.umich.edu// value 956329Sgblack@eecs.umich.educonst int SyscallPseudoReturnReg = INTREG_RDX; 966329Sgblack@eecs.umich.edu 976329Sgblack@eecs.umich.edutypedef uint64_t IntReg; 986329Sgblack@eecs.umich.edu//XXX Should this be a 128 bit structure for XMM memory ops? 996329Sgblack@eecs.umich.edutypedef uint64_t LargestRead; 1006329Sgblack@eecs.umich.edutypedef uint64_t MiscReg; 1016329Sgblack@eecs.umich.edu 1026329Sgblack@eecs.umich.edu//These floating point types are correct for mmx, but not 1036329Sgblack@eecs.umich.edu//technically for x87 (80 bits) or at all for xmm (128 bits) 1046329Sgblack@eecs.umich.edutypedef double FloatReg; 1056329Sgblack@eecs.umich.edutypedef uint64_t FloatRegBits; 1066329Sgblack@eecs.umich.edutypedef union 1076329Sgblack@eecs.umich.edu{ 1086329Sgblack@eecs.umich.edu IntReg intReg; 1096329Sgblack@eecs.umich.edu FloatReg fpReg; 1106329Sgblack@eecs.umich.edu MiscReg ctrlReg; 1116329Sgblack@eecs.umich.edu} AnyReg; 1126329Sgblack@eecs.umich.edu 1136329Sgblack@eecs.umich.edutypedef uint16_t RegIndex; 1144137SN/A 1157811Ssteve.reinhardt@amd.com} // namespace X86ISA 1164120SN/A 1174120SN/A#endif // __ARCH_X86_REGFILE_HH__ 118