/gem5/src/mem/cache/prefetch/ |
H A D | associative_set.hh | 46 /** Whether this entry refers to a memory area in the secure space */ 47 bool secure; member in class:TaggedEntry 49 TaggedEntry() : tag(0), valid(false), secure(false) {} 95 * Consult if this entry refers to a memory in the secure area 96 * @return True if this entry refers to secure memory area 100 return secure; 104 * Sets the secure value bit 105 * @param s secure bit value 109 secure = s;
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H A D | indirect_memory.hh | 72 /** Whether this address is in the secure region */ 73 bool secure; member in struct:IndirectMemoryPrefetcher::PrefetchTableEntry 98 : TaggedEntry(), address(0), secure(false), streamCounter(0), 106 secure = false;
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H A D | base.hh | 101 /** Whether this address targets the secure memory space. */ 102 bool secure; member in class:BasePrefetcher::PrefetchInfo 125 * Returns true if the address targets the secure memory space. 126 * @return true if the address targets the secure memory space. 130 return secure;
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H A D | base.cc | 62 secure(pkt->isSecure()), size(pkt->req->getSize()), write(pkt->isWrite()), 77 secure(pfi.secure), size(pfi.size), write(pfi.write),
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H A D | indirect_memory.cc | 101 pt_entry->secure = is_secure; 163 pt_entry->secure = is_secure;
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/gem5/src/arch/arm/ |
H A D | miscregs.cc | 991 bool secure = !scr.ns; local 997 canRead = secure ? miscRegInfo[reg][MISCREG_USR_S_RD] : 1006 canRead = secure ? miscRegInfo[reg][MISCREG_PRI_S_RD] : 1010 canRead = secure ? miscRegInfo[reg][MISCREG_MON_NS0_RD] : 1027 bool secure = !scr.ns; local 1033 canWrite = secure ? miscRegInfo[reg][MISCREG_USR_S_WR] : 1042 canWrite = secure ? miscRegInfo[reg][MISCREG_PRI_S_WR] : 1046 canWrite = secure ? miscRegInfo[reg][MISCREG_MON_NS0_WR] : 1136 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; local 1140 return secure 1180 bool secure = ArmSystem::haveSecurity(tc) && !scr.ns; local [all...] |
H A D | table_walker.hh | 82 virtual bool secure(bool have_security, WalkerState *currState) const = 0; 230 * Returns true if this entry targets the secure physical address 233 bool secure(bool have_security, WalkerState *currState) const function in class:ArmISA::TableWalker::L1Descriptor 283 bool secure(bool have_security, WalkerState *currState) const function in class:ArmISA::TableWalker::L2Descriptor 285 return l1Parent->secure(have_security, currState); 414 * Returns true if this entry targets the secure physical address 417 bool secure(bool have_security, WalkerState *currState) const 647 /** Whether the subsequent levels of lookup are secure */ 756 /** If the access comes from the secure state. */ 909 bool timing, bool functional, bool secure, [all...] |
H A D | pmu.cc | 503 const bool secure(inSecureState(scr, cpsr)); 507 return secure ? filter.u : (filter.u != filter.nsu); 510 return secure ? filter.p : (filter.p != filter.nsk);
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H A D | tlb.hh | 90 * @param is_secure Access from secure state 207 * @param secure if the lookup is secure 214 bool secure, bool functional, 252 * @param secure_lookup if the operation affects the secure world 257 /** Remove all entries in the non secure world, depending on whether they 275 * @param secure_lookup if the operation affects the secure world 282 * @param secure_lookup if the operation affects the secure world 289 * @param secure_lookup if the operation affects the secure world 297 * @param secure_lookup if the operation affects the secure worl [all...] |
H A D | tlb.cc | 152 TLB::lookup(Addr va, uint16_t asn, uint8_t vmid, bool hyp, bool secure, argument 161 if ((!ignore_asn && table[x].match(va, asn, vmid, hyp, secure, false, 163 (ignore_asn && table[x].match(va, vmid, hyp, secure, target_el))) { 180 DPRINTF(TLBVerbose, "Lookup %#x, asn %#x -> %s vmn 0x%x hyp %d secure %d " 183 va, asn, retval ? "hit" : "miss", vmid, hyp, secure, 243 (secure_lookup ? "secure" : "non-secure")); 307 "secure" : "non-secure")); 316 (secure_lookup ? "secure" [all...] |
H A D | isa.hh | 327 chain secure(bool v = true) const { function in class:ArmISA::ISA::MiscRegLUTEntryInitializer
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H A D | table_walker.cc | 193 bool secure, TLB::ArmTranslationType tranType, 255 currState->isSecure = secure; 2065 te.ns = !descriptor.secure(haveSecurity, currState) || isStage2; 190 walk(const RequestPtr &_req, ThreadContext *_tc, uint16_t _asid, uint8_t _vmid, bool _isHyp, TLB::Mode _mode, TLB::Translation *_trans, bool _timing, bool _functional, bool secure, TLB::ArmTranslationType tranType, bool _stage2Req) argument
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