/gem5/src/arch/riscv/insts/ |
H A D | bitfields.hh | 6 #define CSRIMM bits(machInst, 19, 15) 7 #define FUNCT12 bits(machInst, 31, 20) 8 #define IMM5 bits(machInst, 11, 7) 9 #define IMM7 bits(machInst, 31, 25) 10 #define IMMSIGN bits(machInst, 31) 11 #define OPCODE bits(machInst, 6, 0)
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H A D | unknown.hh | 62 return std::make_shared<UnknownInstFault>(machInst);
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/gem5/src/arch/x86/ |
H A D | emulenv.cc | 48 void EmulEnv::doModRM(const ExtMachInst & machInst) argument 50 assert(machInst.modRM.mod != 3); 52 if (machInst.modRM.rm == 4 && machInst.addrSize != 2) { 53 scale = 1 << machInst.sib.scale; 54 index = machInst.sib.index | (machInst.rex.x << 3); 55 base = machInst.sib.base | (machInst.rex.b << 3); 58 if (machInst 115 setSeg(const ExtMachInst & machInst) argument [all...] |
H A D | types.cc | 40 paramOut(CheckpointOut &cp, const string &name, ExtMachInst const &machInst) argument 43 paramOut(cp, name + ".legacy", (uint8_t)machInst.legacy); 44 paramOut(cp, name + ".rex", (uint8_t)machInst.rex); 45 paramOut(cp, name + ".vex", (uint32_t)machInst.vex); 48 paramOut(cp, name + ".opcode.type", (uint8_t)machInst.opcode.type); 49 paramOut(cp, name + ".opcode.op", (uint8_t)machInst.opcode.op); 52 paramOut(cp, name + ".modRM", (uint8_t)machInst.modRM); 53 paramOut(cp, name + ".sib", (uint8_t)machInst.sib); 56 paramOut(cp, name + ".immediate", machInst.immediate); 57 paramOut(cp, name + ".displacement", machInst 71 paramIn(CheckpointIn &cp, const string &name, ExtMachInst &machInst) argument [all...] |
H A D | emulenv.hh | 71 void doModRM(const ExtMachInst & machInst); 72 void setSeg(const ExtMachInst & machInst);
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/gem5/src/arch/arm/insts/ |
H A D | pred_inst.cc | 51 unsigned rotate = machInst.rotate * 2; 52 uint32_t imm = machInst.imm; 54 printDataInst(ss, false, machInst.opcode4 == 0, machInst.sField, 55 (IntRegIndex)(uint32_t)machInst.rd, 56 (IntRegIndex)(uint32_t)machInst.rn, 57 (IntRegIndex)(uint32_t)machInst.rm, 58 (IntRegIndex)(uint32_t)machInst.rs, 59 machInst.shiftSize, (ArmShiftType)(uint32_t)machInst [all...] |
H A D | macromem.cc | 56 MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst, argument 60 PredMacroOp(mnem, machInst, __opClass) 100 *uop++ = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0); 127 *uop = new MicroLdr2Uop(machInst, reg_idx1, reg_idx2, 157 *uop = new MicroLdrUop(machInst, INTREG_UREG1, 161 *uop = new MicroLdrRetUop(machInst, reg_idx, 165 *uop = new MicroLdrUop(machInst, reg_idx, 180 *uop = new MicroStrUop(machInst, reg_idx, rn, up, addr); 195 *uop++ = new MicroAddiUop(machInst, rn, rn, ones * 4); 197 *uop++ = new MicroSubiUop(machInst, r 242 PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, uint32_t size, bool fp, bool load, bool noAlloc, bool signExt, bool exclusive, bool acrel, int64_t imm, AddrMode mode, IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) argument 347 BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) argument 368 BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) argument 394 BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) argument 420 BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool load, IntRegIndex dest, IntRegIndex base, IntRegIndex offset, ArmExtendType type, int64_t imm) argument 446 BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex dest, int64_t imm) argument 459 VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm) argument 554 VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane) argument 822 VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm) argument 917 VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, bool all, unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, unsigned inc, uint32_t size, uint32_t align, RegIndex rm, unsigned lane) argument 1120 VldMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb) argument 1205 VstMultOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t numRegs, bool wb) argument 1290 VldSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate) argument 1364 VstSingleOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex rn, RegIndex vd, RegIndex rm, uint8_t eSize, uint8_t dataSize, uint8_t numStructElems, uint8_t index, bool wb, bool replicate) argument 1437 MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex rn, RegIndex vd, bool single, bool up, bool writeback, bool load, uint32_t offset) argument [all...] |
H A D | macromem.hh | 69 MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass) argument 70 : PredOp(mnem, machInst, __opClass) 91 MicroOpX(const char *mnem, ExtMachInst machInst, OpClass __opClass) argument 92 : ArmStaticInst(mnem, machInst, __opClass) 119 MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, argument 121 : MicroOp(mnem, machInst, __opClass), 137 MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, argument 139 : MicroOp(mnem, machInst, __opClass), 150 MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst, argument 153 : MicroNeonMixOp(mnem, machInst, __opClas 168 MicroNeonMixOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems, uint8_t _numRegs, uint8_t _step) argument 186 MicroNeonMixLaneOp64(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dest, RegIndex _op1, uint8_t _eSize, uint8_t _dataSize, uint8_t _numStructElems, uint8_t _lane, uint8_t _step, bool _replicate = false) argument 259 MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc) argument 278 MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb) argument 298 MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, int32_t _imm) argument 315 MicroIntImmXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, int64_t _imm) argument 334 MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc) argument 352 MicroIntRegXOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc, ArmExtendType _type, uint32_t _shiftAmt) argument 375 MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, RegIndex _urc, int32_t _shiftAmt, ArmShiftType _shiftType) argument 394 MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm) argument 413 MicroMemPairOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, RegIndex _dreg1, RegIndex _dreg2, RegIndex _base, bool _up, uint8_t _imm) argument [all...] |
H A D | sve_macromem.hh | 61 SveLdStructSS(const char* mnem, ExtMachInst machInst, OpClass __opClass, argument 64 : PredMacroOp(mnem, machInst, __opClass), 73 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i), 78 mnem, machInst, static_cast<IntRegIndex>((_dest + i) % 32), 132 SveStStructSS(const char* mnem, ExtMachInst machInst, OpClass __opClass, argument 135 : PredMacroOp(mnem, machInst, __opClass), 144 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i), 150 mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i), 205 SveLdStructSI(const char* mnem, ExtMachInst machInst, OpClass __opClass, argument 208 : PredMacroOp(mnem, machInst, __opClas 277 SveStStructSI(const char* mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, int64_t _imm, uint8_t _numregs) argument 349 SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, uint64_t _imm, bool firstFault) argument 449 SveIndexedMemSV(const char *mnem, ExtMachInst machInst, OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base, IntRegIndex _offset, bool _offsetIs32, bool _offsetIsSigned, bool _offsetIsScaled, bool firstFault) argument [all...] |
H A D | branch.hh | 73 if (!machInst.itstateMask) 102 if (!machInst.itstateMask)
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H A D | pred_inst.hh | 221 if (machInst.aarch64) 223 else if (machInst.itstateMask) 224 condCode = (ConditionCode)(uint8_t)machInst.itstateCond; 226 condCode = (ConditionCode)(unsigned)machInst.condCode; 245 imm(machInst.imm), rotated_imm(0), rotated_carry(0), 246 rotate(machInst.rotate << 1) 270 shift_size(machInst.shiftSize), shift(machInst.shift)
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H A D | static_inst.cc | 382 printCondition(os, machInst.condCode); 389 if (machInst.bigThumb) 639 return std::make_shared<SoftwareBreakpoint>(machInst, imm); 652 return std::make_shared<SupervisorTrap>(machInst, 0x1E00000, 655 return std::make_shared<HypervisorTrap>(machInst, 0x1E00000, 658 return std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000, 754 machInst, iss, 758 machInst, iss, 825 machInst, iss, 828 return std::make_shared<HypervisorTrap>(machInst, is [all...] |
H A D | pseudo.cc | 66 if (machInst.aarch64) { 133 return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
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H A D | static_inst.hh | 150 aarch64 = machInst.aarch64; 151 if (bits(machInst, 28, 24) == 0x10) 154 intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32; 367 return std::make_shared<UndefinedInstruction>(machInst, false, 523 return (!machInst.thumb || machInst.bigThumb) ? 4 : 2; 528 * the machInst field is in fact always 64 bit wide and 535 return static_cast<MachInst>(machInst & (mask(instSize() * 8))); 541 return simpleAsBytes(buf, max_size, machInst);
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/gem5/src/arch/power/insts/ |
H A D | condition.hh | 54 ba(machInst.ba), 55 bb(machInst.bb), 56 bt(machInst.bt) 77 bf(machInst.bf), 78 bfa(machInst.bfa)
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H A D | integer.hh | 112 imm(sext<16>(machInst.si)), 113 uimm(machInst.si) 134 sh(machInst.sh) 157 mb(machInst.mb), 158 me(machInst.me)
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H A D | branch.hh | 81 disp(machInst.li << 2) 111 targetAddr(machInst.li << 2) 142 bo(machInst.bo), 143 bi(machInst.bi) 190 disp(machInst.bd << 2) 220 targetAddr(machInst.bd << 2)
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H A D | mem.hh | 72 : MemOp(mnem, _machInst, __opClass), disp(machInst.d)
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H A D | static_inst.hh | 76 return simpleAsBytes(buf, max_size, machInst);
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/gem5/src/arch/power/ |
H A D | decoder.hh | 77 moreBytes(MachInst machInst) argument 79 moreBytes(0, 0, machInst);
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/gem5/src/arch/hsail/ |
H A D | gpu_decoder.hh | 56 GPUStaticInst* decode(MachInst machInst);
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/gem5/src/arch/generic/ |
H A D | decode_cache.cc | 46 if (si && (si->machInst == mach_inst))
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/gem5/src/arch/x86/insts/ |
H A D | macroop.hh | 96 return machInst;
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/gem5/src/arch/sparc/insts/ |
H A D | unimp.hh | 68 mnemonic, machInst);
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/gem5/src/arch/alpha/ |
H A D | faults.cc | 163 MachInst machInst = inst->machInst; local 165 (((Opcode(machInst) & 0x3f) << 11) | 166 ((Ra(machInst) & 0x1f) << 6) |
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