Searched refs:dma_ports (Results 1 - 13 of 13) sorted by relevance
/gem5/configs/ruby/ |
H A D | Garnet_standalone.py | 45 def create_system(options, full_system, system, dma_ports, bootmem, 55 assert(dma_ports == [])
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H A D | MI_example.py | 45 def create_system(options, full_system, system, dma_ports, bootmem, 150 for i, dma_port in enumerate(dma_ports): 177 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 179 io_controller = DMA_Controller(version = len(dma_ports),
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H A D | MESI_Two_Level.py | 46 def create_system(options, full_system, system, dma_ports, bootmem, 193 for i, dma_port in enumerate(dma_ports): 219 io_seq = DMASequencer(version = len(dma_ports), 222 io_controller = DMA_Controller(version = len(dma_ports),
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H A D | MOESI_CMP_directory.py | 63 def create_system(options, full_system, system, dma_ports, bootmem, 217 for i, dma_port in enumerate(dma_ports): 251 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 253 io_controller = DMA_Controller(version = len(dma_ports),
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H A D | MOESI_hammer.py | 56 def create_system(options, full_system, system, dma_ports, bootmem, 214 for i, dma_port in enumerate(dma_ports): 244 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 246 io_controller = DMA_Controller(version = len(dma_ports),
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H A D | MOESI_CMP_token.py | 53 def create_system(options, full_system, system, dma_ports, bootmem, 222 for i, dma_port in enumerate(dma_ports): 252 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 254 io_controller = DMA_Controller(version = len(dma_ports),
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H A D | MESI_Three_Level.py | 53 def create_system(options, full_system, system, dma_ports, bootmem, 219 for i, dma_port in enumerate(dma_ports): 249 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 251 io_controller = DMA_Controller(version = len(dma_ports),
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H A D | Ruby.py | 157 def create_system(options, full_system, system, piobus = None, dma_ports = [], 175 eval("%s.create_system(options, full_system, system, dma_ports,\
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/gem5/configs/example/ |
H A D | ruby_mem_test.py | 125 dma_ports = [] variable 127 dma_ports.append(dma.test) 128 Ruby.create_system(options, False, system, dma_ports = dma_ports)
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/gem5/src/dev/x86/ |
H A D | Pc.py | 78 def attachIO(self, bus, dma_ports = []): 79 self.south_bridge.attachIO(bus, dma_ports)
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H A D | SouthBridge.py | 88 def attachIO(self, bus, dma_ports): 105 if dma_ports.count(self.ide.dma) == 0:
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/gem5/configs/common/ |
H A D | FSConfig.py | 106 # Append an underscore to dma_ports to avoid the SimObjectVector check. 368 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) 369 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) 379 dma_ports=self._dma_ports if ruby else None)
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/gem5/src/dev/arm/ |
H A D | RealView.py | 553 def _attach_device(self, device, bus, dma_ports=None): 557 if dma_ports is None: 560 dma_ports.append(device.dma)
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