/gem5/src/kern/ |
H A D | system_events.cc | 41 using namespace TheISA; 46 TheISA::PCState oldPC M5_VAR_USED = tc->pcState(); 49 TheISA::skipFunction(tc);
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/gem5/src/arch/generic/ |
H A D | decode_cache.hh | 39 namespace TheISA namespace 50 DecodeCache::InstMap<TheISA::ExtMachInst> instMap; 57 StaticInstPtr decode(TheISA::Decoder * const decoder, 58 TheISA::ExtMachInst mach_inst, Addr addr);
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H A D | traits.hh | 59 mode(const TheISA::PCState&) argument
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H A D | decode_cache.cc | 42 BasicDecodeCache::decode(TheISA::Decoder *decoder, 43 TheISA::ExtMachInst mach_inst, Addr addr)
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/gem5/src/cpu/pred/ |
H A D | ras.hh | 57 TheISA::PCState top() 65 void push(const TheISA::PCState &return_addr); 75 void restore(unsigned top_entry_idx, const TheISA::PCState &restored); 90 std::vector<TheISA::PCState> addrStack;
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H A D | btb.hh | 52 TheISA::PCState target; 78 TheISA::PCState lookup(Addr instPC, ThreadID tid); 92 void update(Addr instPC, const TheISA::PCState &targetPC,
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H A D | ras.cc | 51 ReturnAddrStack::push(const TheISA::PCState &return_addr) 74 const TheISA::PCState &restored)
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H A D | indirect.hh | 51 virtual bool lookup(Addr br_addr, TheISA::PCState& br_target, 59 const TheISA::PCState& target, ThreadID tid) = 0;
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/gem5/src/cpu/ |
H A D | static_inst.cc | 40 static TheISA::ExtMachInst nopMachInst; 55 advancePC(TheISA::PCState &pcState) const override 83 StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc, 84 TheISA::PCState &tgt) const 106 TheISA::PCState 107 StaticInst::branchTarget(const TheISA::PCState &pc) const 114 TheISA::PCState
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H A D | decode_cache.hh | 41 namespace TheISA namespace 60 Value items[TheISA::PageBytes]; 85 Addr page_addr = addr & ~(TheISA::PageBytes - 1); 108 page_addr = page_addr & ~(TheISA::PageBytes - 1); 125 return page->items[addr & (TheISA::PageBytes - 1)];
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H A D | inteltrace.hh | 49 const StaticInstPtr _staticInst, TheISA::PCState _pc, 68 const StaticInstPtr staticInst, TheISA::PCState pc,
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H A D | thread_context.cc | 64 for (int i = 0; i < TheISA::NumIntRegs; ++i) { 73 for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 82 for (int i = 0; i < TheISA::NumVecRegs; ++i) { 84 const TheISA::VecRegContainer& t1 = one->readVecReg(rid); 85 const TheISA::VecRegContainer& t2 = two->readVecReg(rid); 92 for (int i = 0; i < TheISA::NumVecPredRegs; ++i) { 94 const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid); 95 const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid); 101 for (int i = 0; i < TheISA::NumMiscRegs; ++i) { 110 for (int i = 0; i < TheISA [all...] |
H A D | simple_thread.hh | 98 typedef TheISA::MachInst MachInst; 99 using VecRegContainer = TheISA::VecRegContainer; 100 using VecElem = TheISA::VecElem; 101 using VecPredRegContainer = TheISA::VecPredRegContainer; 106 RegVal floatRegs[TheISA::NumFloatRegs]; 107 RegVal intRegs[TheISA::NumIntRegs]; 108 VecRegContainer vecRegs[TheISA::NumVecRegs]; 109 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs]; 111 RegVal ccRegs[TheISA::NumCCRegs]; 113 TheISA [all...] |
H A D | exetrace.hh | 51 const StaticInstPtr _staticInst, TheISA::PCState _pc, 72 const StaticInstPtr staticInst, TheISA::PCState pc,
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H A D | inteltrace.cc | 43 using namespace TheISA;
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/gem5/src/mem/ |
H A D | fs_translating_port_proxy.cc | 79 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done(); 83 paddr = TheISA::vtophys(_tc,gen.addr()); 85 paddr = TheISA::vtophys(gen.addr()); 98 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done(); 102 paddr = TheISA::vtophys(_tc,gen.addr()); 104 paddr = TheISA::vtophys(gen.addr()); 116 for (ChunkGenerator gen(address, size, TheISA::PageBytes); !gen.done(); 120 paddr = TheISA::vtophys(_tc,gen.addr()); 122 paddr = TheISA::vtophys(gen.addr());
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/gem5/src/cpu/minor/ |
H A D | scoreboard.hh | 96 numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs + 97 TheISA::NumFloatRegs + 98 (TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg) + 99 TheISA::NumVecPredRegs),
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H A D | scoreboard.cc | 66 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs + 71 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs + 72 TheISA::NumFloatRegs + reg.index(); 76 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs + 77 TheISA::NumFloatRegs + reg.flatIndex(); 81 scoreboard_index = TheISA::NumIntRegs + TheISA [all...] |
/gem5/src/cpu/o3/ |
H A D | rename_map.cc | 121 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg); 123 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg); 125 vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1); 127 vecElemMap.init(TheISA::NumVecRegs * NVecElems, 130 predMap.init(TheISA::NumVecPredRegs, &(freeList->predList), (RegIndex)-1); 132 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1); 145 regFile->numVecPhysRegs() - TheISA::NumVecRegs, 162 TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg, 166 freeList->addRegs(range.first + TheISA [all...] |
H A D | impl.hh | 56 typedef TheISA::MachInst MachInst;
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/gem5/src/sim/ |
H A D | insttracer.hh | 69 TheISA::PCState pc; 100 ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec; 101 ::VecPredRegContainer<TheISA::VecPredRegSizeBits, 102 TheISA::VecPredRegHasPackedRepr>* as_pred; 152 TheISA::PCState _pc, 201 setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d) 203 data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d); 208 setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits, 209 TheISA::VecPredRegHasPackedRepr>& d) 212 TheISA [all...] |
H A D | arguments.cc | 55 return TheISA::getArgument(tc, number, size, fp);
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/gem5/src/kern/freebsd/ |
H A D | events.cc | 56 uint64_t time = TheISA::getArgument(tc, arg_num, (uint16_t)-1, false);
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/gem5/src/kern/linux/ |
H A D | helpers.cc | 70 de.ts_nsec = TheISA::gtoh(de.ts_nsec); 71 de.len = TheISA::gtoh(de.len); 72 de.text_len = TheISA::gtoh(de.text_len); 112 proxy.read<uint32_t>(addr_lb_len, TheISA::GuestByteOrder); 114 proxy.read<uint32_t>(addr_first, TheISA::GuestByteOrder); 116 proxy.read<uint32_t>(addr_next, TheISA::GuestByteOrder);
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/gem5/src/dev/arm/ |
H A D | realview.cc | 59 using namespace TheISA;
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