Searched refs:MISCREG_SCR (Results 1 - 11 of 11) sorted by relevance

/gem5/src/arch/arm/
H A Disa.cc256 miscRegs[MISCREG_SCR] = 0;
260 miscRegs[MISCREG_SCR] = 1;
497 scr = readMiscRegNoEffect(MISCREG_SCR);
523 scr = readMiscRegNoEffect(MISCREG_SCR);
678 readMiscRegNoEffect(MISCREG_SCR));
694 inSecureState(readMiscRegNoEffect(MISCREG_SCR),
840 scr = readMiscRegNoEffect(MISCREG_SCR);
1050 case MISCREG_SCR:
1057 scr = readMiscRegNoEffect(MISCREG_SCR);
1112 scr = readMiscReg(MISCREG_SCR, t
[all...]
H A Dfaults.cc499 SCR scr = tc->readMiscReg(MISCREG_SCR);
518 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
521 tc->setMiscRegNoEffect(MISCREG_SCR, scr);
798 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
870 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1180 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1274 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1284 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1335 scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1345 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
[all...]
H A Dinterrupts.cc65 scr = tc->readMiscReg(MISCREG_SCR);
H A Disa.hh646 inSecureState(miscRegs[MISCREG_SCR],
651 !inSecureState(miscRegs[MISCREG_SCR],
679 inSecureState(miscRegs[MISCREG_SCR],
H A Dutility.cc199 tc->readMiscReg(MISCREG_SCR);
474 const SCR scr = tc->readMiscReg(MISCREG_SCR);
H A Dpmu.cc500 const SCR scr(pmu.isa->readMiscRegNoEffect(MISCREG_SCR));
H A Dmiscregs.hh179 MISCREG_SCR, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc239 return MISCREG_SCR;
1063 SCR scr = tc->readMiscReg(MISCREG_SCR);
1081 SCR scr = tc->readMiscReg(MISCREG_SCR);
3199 InitReg(MISCREG_SCR)
4031 .mapsTo(MISCREG_SCR); // NAM D7-2005
H A Dtlb.cc1372 scr = tc->readMiscReg(MISCREG_SCR);
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc164 { "scr", MISCREG_SCR },
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc2332 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);

Completed in 45 milliseconds