Searched refs:MISCREG_ICIALLU (Results 1 - 5 of 5) sorted by relevance

/gem5/src/arch/arm/insts/
H A Dmisc64.cc200 case MISCREG_ICIALLU:
/gem5/src/arch/arm/
H A Dutility.cc532 case MISCREG_ICIALLU:
H A Dmiscregs.hh232 MISCREG_ICIALLU, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc364 return MISCREG_ICIALLU;
3364 InitReg(MISCREG_ICIALLU)
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc206 { "iciallu", MISCREG_ICIALLU },

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