| /gem5/src/arch/alpha/ |
| H A D | tlb.cc | 383 req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
389 req->setPaddr(req->getVaddr());
392 if (!validVirtualAddress(req->getVaddr())) {
394 return std::make_shared<ItbAcvFault>(req->getVaddr());
400 if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
405 return std::make_shared<ItbAcvFault>(req->getVaddr());
408 req->setPaddr(req->getVaddr() & PAddrImplMask);
418 TlbEntry *entry = lookup(VAddr(req->getVaddr()).vpn(),
423 return std::make_shared<ItbPageFault>(req->getVaddr());
427 (VAddr(req->getVaddr())
[all...] |
| /gem5/src/mem/ |
| H A D | page_table.cc | 160 assert(pageAlign(req->getVaddr() + req->getSize() - 1) ==
161 pageAlign(req->getVaddr()));
162 if (!translate(req->getVaddr(), paddr))
163 return Fault(new GenericPageTableFault(req->getVaddr()));
|
| /gem5/src/cpu/checker/ |
| H A D | cpu.cc | 205 flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
250 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
289 flags_match = checkFlags(unverifiedReq, mem_req->getVaddr(),
318 curTick(), unverifiedReq->getVaddr(), unverifiedReq->getPaddr(),
373 Addr unverifiedVAddr = unverified_req->getVaddr();
|
| /gem5/src/arch/riscv/ |
| H A D | tlb.cc | 152 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
301 req->setPaddr(req->getVaddr());
336 req->setPaddr(req->getVaddr());
354 if (req->getVaddr() + req->getSize() - 1 < req->getVaddr())
355 return make_shared<GenericPageTableFault>(req->getVaddr());
|
| /gem5/src/arch/arm/ |
| H A D | stage2_lookup.hh | 86 req->setVirt(0, s1Te.pAddr(s1Req->getVaddr()), s1Req->getSize(),
|
| H A D | stage2_lookup.cc | 97 stage1Te.vpn = s1Req->getVaddr() >> stage2Te->N;
173 s1Req->getVaddr());
|
| H A D | tlb.cc | 569 Addr vaddr_tainted = req->getVaddr();
613 Addr vaddr = req->getVaddr(); // 32-bit don't have to purify
797 Addr vaddr_tainted = req->getVaddr();
1045 Addr vaddr_tainted = req->getVaddr();
1464 Addr vaddr_tainted = req->getVaddr();
1546 Addr vaddr_tainted = req->getVaddr();
|
| /gem5/src/gpu-compute/ |
| H A D | tlb_coalescer.cc | 110 Addr incoming_virt_page_addr = roundDown(incoming_pkt->req->getVaddr(),
113 Addr coalesced_virt_page_addr = roundDown(coalesced_pkt->req->getVaddr(),
144 Addr virt_page_addr = roundDown(pkt->req->getVaddr(), TheISA::PageBytes);
185 paddr |= (local_pkt->req->getVaddr() & (page_size - 1));
350 Addr virt_page_addr = roundDown(pkt->req->getVaddr(), TheISA::PageBytes);
434 Addr virt_page_addr = roundDown(first_packet->req->getVaddr(),
|
| H A D | gpu_tlb.cc | 280 Addr vaddr = req->getVaddr();
662 Addr vaddr = req->getVaddr();
716 Addr vaddr = req->getVaddr();
1038 Addr virt_page_addr = roundDown(pkt->req->getVaddr(),
1068 TlbEntry *entry = lookup(tmp_req->getVaddr(), false);
1164 Addr vaddr = pkt->req->getVaddr();
1323 Addr vaddr = pkt->req->getVaddr();
1417 Addr vaddr = pkt->req->getVaddr();
1488 Addr virt_page_addr = roundDown(pkt->req->getVaddr(),
1525 Addr vaddr = pkt->req->getVaddr();
[all...] |
| H A D | compute_unit.cc | 746 Addr tmp_vaddr = pkt->req->getVaddr();
777 Addr vaddr = pkt->req->getVaddr();
1074 pkt->req->getVaddr(), line);
1093 pkt->req->getVaddr());
1115 Addr vaddr = pkt->req->getVaddr();
1299 Addr vaddr M5_VAR_USED = pkt->req->getVaddr();
1319 computeUnit->cu_id, pkt->req->getVaddr(), line);
1383 Addr vaddr M5_VAR_USED = pkt->req->getVaddr();
|
| H A D | shader.cc | 246 tmp_addr = req->getVaddr();
|
| /gem5/src/arch/power/ |
| H A D | tlb.cc | 151 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
285 if (req->getVaddr() & 0x3) {
286 DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
|
| /gem5/src/mem/cache/prefetch/ |
| H A D | queued.cc | 282 it->translationRequest->getVaddr(),
300 it->translationRequest->getVaddr());
377 pkt->req->getVaddr() : pkt->req->getPaddr();
409 // Compute the target VA using req->getVaddr + stride
411 (pkt->req->getVaddr() + stride) :
412 (pkt->req->getVaddr() - stride);
|
| H A D | base.cc | 221 PrefetchInfo pfi(pkt, pkt->req->getVaddr(), miss);
|
| /gem5/src/cpu/minor/ |
| H A D | fetch1.cc | 263 response->request->getVaddr());
405 response->id, request->getVaddr());
408 response->id, request->getVaddr(), response->fault->name());
412 request->getVaddr(), request->getPaddr());
554 line.lineBaseAddr = response->request->getVaddr();
|
| H A D | lsq.cc | 414 Addr base_addr = request->getVaddr();
536 Addr base_addr = request->getVaddr();
552 Addr fragment_addr = fragment->getVaddr();
631 response->req->getVaddr(), response->req->getSize(),
632 request->getVaddr() - response->req->getVaddr(),
658 data + (response->req->getVaddr() - request->getVaddr()),
1175 *(request->inst), packet->req->getVaddr());
|
| /gem5/src/cpu/o3/ |
| H A D | lsq_unit.hh | 700 auto req_s = req->mainRequest()->getVaddr();
719 int shift_amt = req->mainRequest()->getVaddr() -
737 req->mainRequest()->getVaddr());
811 store_it._idx, req->mainRequest()->getVaddr());
|
| H A D | fetch_impl.hh | 658 Addr fetchBufferBlockPC = mem_req->getVaddr();
666 mem_req->getVaddr() != memReq[tid]->getVaddr()) {
728 tid, mem_req->getVaddr(), memReq[tid]->getVaddr());
|
| H A D | lsq.hh | 483 Addr getVaddr(int idx = 0) const { return request(idx)->getVaddr(); } function
|
| H A D | lsq_impl.hh | 739 inst->effAddr = req->getVaddr();
1059 ptrdiff_t offset = r->getVaddr() - base_address;
|
| /gem5/src/arch/x86/ |
| H A D | tlb.cc | 176 Addr vaddr = req->getVaddr();
285 Addr vaddr = req->getVaddr();
|
| H A D | pagetable_walker.cc | 201 currState->req->getVaddr());
233 setupWalk(req->getVaddr());
|
| /gem5/src/arch/mips/ |
| H A D | tlb.cc | 150 if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
|
| /gem5/src/arch/sparc/ |
| H A D | tlb.cc | 423 Addr vaddr = req->getVaddr();
511 req->getVaddr());
540 Addr vaddr = req->getVaddr();
728 req->getVaddr());
832 req->setPaddr(req->getVaddr());
|
| /gem5/src/cpu/simple/ |
| H A D | timing.cc | 683 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
702 req->getVaddr(), req->getPaddr());
717 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
|