Searched refs:x3 (Results 1 - 25 of 76) sorted by relevance

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/gem5/src/systemc/tests/systemc/misc/examples/a2901/
H A Da2901_alu_inputs.cpp56 case 0x3:
70 case 0x3:
H A Da2901_alu.cpp58 case 0x3:
/gem5/src/arch/alpha/
H A Dev5.hh49 inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
77 inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
86 inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
89 inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
92 inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
95 inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
96 inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
97 inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
H A Dpagetable.hh75 int _rsv0() const { return (entry >> 14) & 0x3; }
78 int _rsv1() const { return (entry >> 10) & 0x3; }
82 int _gh() const { return (entry >> 5) & 0x3; }
H A Dutility.hh69 inline bool PcPAL(Addr addr) { return addr & 0x3; }
/gem5/src/arch/riscv/
H A Ddecoder.hh67 inline bool compressed(ExtMachInst inst) { return (inst & 0x3) < 0x3; }
/gem5/src/dev/x86/
H A Di8237.cc49 case 0x3:
84 case 0x3:
H A Di8259.cc136 case 0x3:
214 case 0x3:
/gem5/system/arm/aarch64_bootloader/
H A Dboot.S82 mov x3, #1 << 18 // GICv4
83 mul x3, x3, x2
84 add x1, x1, x3
144 mov x3, xzr
/gem5/ext/libfdt/
H A Dfdt.h85 #define FDT_PROP 0x3 /* Property: name off,
/gem5/src/arch/sparc/insts/
H A Dstatic_inst.hh52 Less=0x3,
73 FUnorderedOrLess=0x3,
/gem5/ext/nomali/lib/
H A Dtypes.hh163 assert((addr.value & 0x3) == 0);
191 assert((cls & ~0x3) == 0);
200 return (StatusClass)((value >> 6) & 0x3);
H A Dmali_midg_regmap.h307 #define ASn_FAULTSTATUS_ACCESS_TYPE_MASK (0x3<<8)
310 #define ASn_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3<<8)
471 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
474 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_READS_SHIFT)
477 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
480 #define L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_HALF (0x3 << L2_MMU_CONFIG_LIMIT_EXTERNAL_WRITES_SHIFT)
/gem5/system/alpha/h/
H A Dev5_paldef.h153 #define osf_a0_fen (0x3)
H A DfromHudsonOsf.h121 #define IF_K_FEN 0x3
131 #define INT_K_DEV 0x3
141 #define MM_K_FOE 0x3
178 #define IPL_K_DEV0 0x3
/gem5/src/dev/pci/
H A DPciHost.py74 spacef = space & 0x3
H A Ddevice.hh61 #define BAR_IO_MASK 0x3
/gem5/src/arch/arm/
H A Dpagetable.hh154 innerAttrs(0), outerAttrs(0), ap(read_only ? 0x3 : 0), hap(0x3),
160 // no restrictions by default, hap = 0x3
169 vmid(0), N(0), innerAttrs(0), outerAttrs(0), ap(0), hap(0x3),
175 // no restrictions by default, hap = 0x3
246 shareable ? 0x3 : 0) << 7);
H A Dprocess.cc113 cpacr.cp10 = 0x3;
114 cpacr.cp11 = 0x3;
135 cpacr.cp10 = 0x3;
136 cpacr.cp11 = 0x3;
138 cpacr.zen = 0x3;
/gem5/src/arch/x86/
H A Dutility.cc294 const unsigned tag((ftw >> (2 * i)) & 0x3);
306 if (tag != 0x3)
323 ftw |= 0x3 << (2 * i);
342 ftw |= 0x3 << (2 * i);
348 ftw &= ~(0x3 << (2 * i));
/gem5/src/base/
H A Dcirclebuf.test.cc45 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
/gem5/src/arch/sparc/
H A Dua2005.cc298 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
303 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
307 ((x & 0x3) * (STS::shft_fsm0-STS::shft_fsm1)));
/gem5/ext/libelf/
H A Delf32.h200 #define ELF32_ST_VISIBILITY(oth) ((oth) & 0x3)
/gem5/src/dev/serial/
H A Duart8250.cc145 case 0x3: // Line Control Register (LCR)
248 case 0x3: // Line Control Register (LCR)
/gem5/tests/test-progs/asmtest/src/riscv/env/v/
H A Dentry.S44 LOAD x3,3*REGBYTES(a0)
81 STORE x3,3*REGBYTES(sp)

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