18012Ssaidi@eecs.umich.edu/*
28029Snate@binkert.org * Copyright (c) 1993-1994 The Hewlett-Packard Development Company
38029Snate@binkert.org * All rights reserved.
48013Sbinkertn@umich.edu *
58029Snate@binkert.org * Redistribution and use in source and binary forms, with or without
68029Snate@binkert.org * modification, are permitted provided that the following conditions are
78029Snate@binkert.org * met: redistributions of source code must retain the above copyright
88029Snate@binkert.org * notice, this list of conditions and the following disclaimer;
98029Snate@binkert.org * redistributions in binary form must reproduce the above copyright
108029Snate@binkert.org * notice, this list of conditions and the following disclaimer in the
118029Snate@binkert.org * documentation and/or other materials provided with the distribution;
128029Snate@binkert.org * neither the name of the copyright holders nor the names of its
138029Snate@binkert.org * contributors may be used to endorse or promote products derived from
148029Snate@binkert.org * this software without specific prior written permission.
158013Sbinkertn@umich.edu *
168029Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
178029Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
188029Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
198029Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
208029Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
218029Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
228029Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
238029Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
248029Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
258029Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
268029Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
278013Sbinkertn@umich.edu */
288012Ssaidi@eecs.umich.edu
297997Ssaidi@eecs.umich.edu#ifndef FROMHUDSONOSF_INCLUDED
307997Ssaidi@eecs.umich.edu#define FROMHUDSONOSF_INCLUDED 1
318013Sbinkertn@umich.edu
327997Ssaidi@eecs.umich.edu#define	__OSF_LOADED	1
337997Ssaidi@eecs.umich.edu/*
347997Ssaidi@eecs.umich.edu**  Seg0 and Seg1 Virtual Address (VA) Format
357997Ssaidi@eecs.umich.edu**
367997Ssaidi@eecs.umich.edu**	  Loc	Size	Name	Function
377997Ssaidi@eecs.umich.edu**	 -----	----	----	---------------------------------
387997Ssaidi@eecs.umich.edu**	<42:33>  10	SEG1	First level page table offset
397997Ssaidi@eecs.umich.edu**	<32:23>  10	SEG2	Second level page table offset
407997Ssaidi@eecs.umich.edu**	<22:13>  10	SEG3	Third level page table offset
417997Ssaidi@eecs.umich.edu**	<12:00>  13	OFFSET	Byte within page offset
427997Ssaidi@eecs.umich.edu*/
437997Ssaidi@eecs.umich.edu
447997Ssaidi@eecs.umich.edu#define VA_V_SEG1	33
457997Ssaidi@eecs.umich.edu#define	VA_M_SEG1	(0x3FF<<VA_V_SEG1)
467997Ssaidi@eecs.umich.edu#define VA_V_SEG2	23
477997Ssaidi@eecs.umich.edu#define VA_M_SEG2	(0x3FF<<VA_V_SEG2)
487997Ssaidi@eecs.umich.edu#define VA_V_SEG3	13
497997Ssaidi@eecs.umich.edu#define VA_M_SEG3	(0x3FF<<VA_V_SEG3)
507997Ssaidi@eecs.umich.edu#define VA_V_OFFSET	0
517997Ssaidi@eecs.umich.edu#define VA_M_OFFSET	0x1FFF
527997Ssaidi@eecs.umich.edu
537997Ssaidi@eecs.umich.edu/*
547997Ssaidi@eecs.umich.edu**  Virtual Address Options: 8K byte page size
557997Ssaidi@eecs.umich.edu*/
567997Ssaidi@eecs.umich.edu
577997Ssaidi@eecs.umich.edu#define	VA_S_SIZE	43
587997Ssaidi@eecs.umich.edu#define	VA_S_OFF	13
597997Ssaidi@eecs.umich.edu#define	va_s_off	13
607997Ssaidi@eecs.umich.edu#define VA_S_SEG	10
617997Ssaidi@eecs.umich.edu#define VA_S_PAGE_SIZE	8192
627997Ssaidi@eecs.umich.edu
637997Ssaidi@eecs.umich.edu/*
647997Ssaidi@eecs.umich.edu**  Page Table Entry (PTE) Format
657997Ssaidi@eecs.umich.edu**
667997Ssaidi@eecs.umich.edu**	 Extent	Size	Name	Function
677997Ssaidi@eecs.umich.edu**	 ------	----	----	---------------------------------
687997Ssaidi@eecs.umich.edu**	<63:32>	  32	PFN	Page Frame Number
697997Ssaidi@eecs.umich.edu**	<31:16>	  16	SW	Reserved for software
707997Ssaidi@eecs.umich.edu**	<15:14>	   2	RSV0	Reserved for hardware SBZ
717997Ssaidi@eecs.umich.edu**	   <13>	   1	UWE	User Write Enable
727997Ssaidi@eecs.umich.edu**	   <12>	   1	KWE	Kernel Write Enable
737997Ssaidi@eecs.umich.edu**	<11:10>	   2	RSV1	Reserved for hardware SBZ
747997Ssaidi@eecs.umich.edu**	    <9>	   1	URE	User Read Enable
757997Ssaidi@eecs.umich.edu**	    <8>	   1	KRE	Kernel Read Enable
767997Ssaidi@eecs.umich.edu**	    <7>	   1	RSV2	Reserved for hardware SBZ
777997Ssaidi@eecs.umich.edu**	  <6:5>	   2	GH	Granularity Hint
787997Ssaidi@eecs.umich.edu**	    <4>	   1	ASM	Address Space Match
797997Ssaidi@eecs.umich.edu**	    <3>	   1	FOE	Fault On Execute
807997Ssaidi@eecs.umich.edu**	    <2>	   1	FOW	Fault On Write
817997Ssaidi@eecs.umich.edu**	    <1>	   1	FOR	Fault On Read
827997Ssaidi@eecs.umich.edu**	    <0>	   1	V	Valid
837997Ssaidi@eecs.umich.edu*/
847997Ssaidi@eecs.umich.edu
857997Ssaidi@eecs.umich.edu#define	PTE_V_PFN	32
867997Ssaidi@eecs.umich.edu#define PTE_M_PFN	0xFFFFFFFF00000000
877997Ssaidi@eecs.umich.edu#define PTE_V_SW	16
887997Ssaidi@eecs.umich.edu#define PTE_M_SW	0x00000000FFFF0000
897997Ssaidi@eecs.umich.edu#define PTE_V_UWE	13
907997Ssaidi@eecs.umich.edu#define PTE_M_UWE	(1<<PTE_V_UWE)
917997Ssaidi@eecs.umich.edu#define PTE_V_KWE	12
927997Ssaidi@eecs.umich.edu#define PTE_M_KWE	(1<<PTE_V_KWE)
937997Ssaidi@eecs.umich.edu#define PTE_V_URE	9
947997Ssaidi@eecs.umich.edu#define PTE_M_URE	(1<<PTE_V_URE)
957997Ssaidi@eecs.umich.edu#define PTE_V_KRE	8
967997Ssaidi@eecs.umich.edu#define PTE_M_KRE	(1<<PTE_V_KRE)
977997Ssaidi@eecs.umich.edu#define PTE_V_GH	5
987997Ssaidi@eecs.umich.edu#define PTE_M_GH	(3<<PTE_V_GH)
997997Ssaidi@eecs.umich.edu#define PTE_V_ASM	4
1007997Ssaidi@eecs.umich.edu#define PTE_M_ASM	(1<<PTE_V_ASM)
1017997Ssaidi@eecs.umich.edu#define PTE_V_FOE	3
1027997Ssaidi@eecs.umich.edu#define PTE_M_FOE	(1<<PTE_V_FOE)
1037997Ssaidi@eecs.umich.edu#define PTE_V_FOW	2
1047997Ssaidi@eecs.umich.edu#define PTE_M_FOW	(1<<PTE_V_FOW)
1057997Ssaidi@eecs.umich.edu#define PTE_V_FOR	1
1067997Ssaidi@eecs.umich.edu#define PTE_M_FOR	(1<<PTE_V_FOR)
1077997Ssaidi@eecs.umich.edu#define PTE_V_VALID	0
1087997Ssaidi@eecs.umich.edu#define PTE_M_VALID	(1<<PTE_V_VALID)
1097997Ssaidi@eecs.umich.edu
1107997Ssaidi@eecs.umich.edu#define PTE_M_KSEG	0x1111
1117997Ssaidi@eecs.umich.edu#define PTE_M_PROT	0x3300
1127997Ssaidi@eecs.umich.edu#define pte_m_prot	0x3300
1137997Ssaidi@eecs.umich.edu
1147997Ssaidi@eecs.umich.edu/*
1157997Ssaidi@eecs.umich.edu**  System Entry Instruction Fault (entIF) Constants:
1167997Ssaidi@eecs.umich.edu*/
1177997Ssaidi@eecs.umich.edu
1187997Ssaidi@eecs.umich.edu#define IF_K_BPT        0x0
1197997Ssaidi@eecs.umich.edu#define IF_K_BUGCHK     0x1
1207997Ssaidi@eecs.umich.edu#define IF_K_GENTRAP    0x2
1217997Ssaidi@eecs.umich.edu#define IF_K_FEN        0x3
1227997Ssaidi@eecs.umich.edu#define IF_K_OPCDEC     0x4
1237997Ssaidi@eecs.umich.edu
1247997Ssaidi@eecs.umich.edu/*
1257997Ssaidi@eecs.umich.edu**  System Entry Hardware Interrupt (entInt) Constants:
1267997Ssaidi@eecs.umich.edu*/
1277997Ssaidi@eecs.umich.edu
1287997Ssaidi@eecs.umich.edu#define INT_K_IP	0x0
1297997Ssaidi@eecs.umich.edu#define INT_K_CLK	0x1
1307997Ssaidi@eecs.umich.edu#define INT_K_MCHK	0x2
1317997Ssaidi@eecs.umich.edu#define INT_K_DEV	0x3
1327997Ssaidi@eecs.umich.edu#define INT_K_PERF	0x4
1337997Ssaidi@eecs.umich.edu
1347997Ssaidi@eecs.umich.edu/*
1357997Ssaidi@eecs.umich.edu**  System Entry MM Fault (entMM) Constants:
1367997Ssaidi@eecs.umich.edu*/
1377997Ssaidi@eecs.umich.edu
1387997Ssaidi@eecs.umich.edu#define	MM_K_TNV	0x0
1397997Ssaidi@eecs.umich.edu#define MM_K_ACV	0x1
1407997Ssaidi@eecs.umich.edu#define MM_K_FOR	0x2
1417997Ssaidi@eecs.umich.edu#define MM_K_FOE	0x3
1427997Ssaidi@eecs.umich.edu#define MM_K_FOW	0x4
1437997Ssaidi@eecs.umich.edu
1447997Ssaidi@eecs.umich.edu/*
1457997Ssaidi@eecs.umich.edu**  Process Control Block (PCB) Offsets:
1467997Ssaidi@eecs.umich.edu*/
1477997Ssaidi@eecs.umich.edu
1487997Ssaidi@eecs.umich.edu#define PCB_Q_KSP	0x0000
1497997Ssaidi@eecs.umich.edu#define PCB_Q_USP	0x0008
1507997Ssaidi@eecs.umich.edu#define PCB_Q_PTBR	0x0010
1517997Ssaidi@eecs.umich.edu#define PCB_L_PCC	0x0018
1527997Ssaidi@eecs.umich.edu#define PCB_L_ASN	0x001C
1537997Ssaidi@eecs.umich.edu#define PCB_Q_UNIQUE	0x0020
1547997Ssaidi@eecs.umich.edu#define PCB_Q_FEN	0x0028
1557997Ssaidi@eecs.umich.edu#define PCB_Q_RSV0	0x0030
1567997Ssaidi@eecs.umich.edu#define PCB_Q_RSV1	0x0038
1577997Ssaidi@eecs.umich.edu
1587997Ssaidi@eecs.umich.edu/*
1597997Ssaidi@eecs.umich.edu**  Processor Status Register (PS) Bit Summary
1607997Ssaidi@eecs.umich.edu**
1617997Ssaidi@eecs.umich.edu**	Extent	Size	Name	Function
1627997Ssaidi@eecs.umich.edu**	------	----	----	---------------------------------
1637997Ssaidi@eecs.umich.edu**	  <3>	 1	CM	Current Mode
1647997Ssaidi@eecs.umich.edu**	<2:0>	 3	IPL	Interrupt Priority Level
1657997Ssaidi@eecs.umich.edu**/
1667997Ssaidi@eecs.umich.edu
1677997Ssaidi@eecs.umich.edu#define	PS_V_CM		3
1687997Ssaidi@eecs.umich.edu#define PS_M_CM		(1<<PS_V_CM)
1697997Ssaidi@eecs.umich.edu#define	PS_V_IPL	0
1707997Ssaidi@eecs.umich.edu#define	PS_M_IPL	(7<<PS_V_IPL)
1717997Ssaidi@eecs.umich.edu
1727997Ssaidi@eecs.umich.edu#define	PS_K_KERN	(0<<PS_V_CM)
1737997Ssaidi@eecs.umich.edu#define PS_K_USER	(1<<PS_V_CM)
1747997Ssaidi@eecs.umich.edu
1757997Ssaidi@eecs.umich.edu#define	IPL_K_ZERO	0x0
1767997Ssaidi@eecs.umich.edu#define IPL_K_SW0	0x1
1777997Ssaidi@eecs.umich.edu#define IPL_K_SW1	0x2
1787997Ssaidi@eecs.umich.edu#define IPL_K_DEV0	0x3
1797997Ssaidi@eecs.umich.edu#define IPL_K_DEV1	0x4
1807997Ssaidi@eecs.umich.edu#define IPL_K_CLK	0x5
1817997Ssaidi@eecs.umich.edu#define IPL_K_RT	0x6
1827997Ssaidi@eecs.umich.edu#define IPL_K_PERF      0x6
1837997Ssaidi@eecs.umich.edu#define IPL_K_PFAIL     0x6
1847997Ssaidi@eecs.umich.edu#define IPL_K_MCHK	0x7
1857997Ssaidi@eecs.umich.edu
1867997Ssaidi@eecs.umich.edu#define IPL_K_LOW	0x0
1877997Ssaidi@eecs.umich.edu#define IPL_K_HIGH	0x7
1887997Ssaidi@eecs.umich.edu
1897997Ssaidi@eecs.umich.edu/*
1907997Ssaidi@eecs.umich.edu**  SCB Offset Definitions:
1917997Ssaidi@eecs.umich.edu*/
1927997Ssaidi@eecs.umich.edu
1937997Ssaidi@eecs.umich.edu#define SCB_Q_FEN	    	0x0010
1947997Ssaidi@eecs.umich.edu#define SCB_Q_ACV		0x0080
1957997Ssaidi@eecs.umich.edu#define SCB_Q_TNV		0x0090
1967997Ssaidi@eecs.umich.edu#define SCB_Q_FOR		0x00A0
1977997Ssaidi@eecs.umich.edu#define SCB_Q_FOW		0x00B0
1987997Ssaidi@eecs.umich.edu#define SCB_Q_FOE		0x00C0
1997997Ssaidi@eecs.umich.edu#define SCB_Q_ARITH		0x0200
2007997Ssaidi@eecs.umich.edu#define SCB_Q_KAST		0x0240
2017997Ssaidi@eecs.umich.edu#define SCB_Q_EAST		0x0250
2027997Ssaidi@eecs.umich.edu#define SCB_Q_SAST		0x0260
2037997Ssaidi@eecs.umich.edu#define SCB_Q_UAST		0x0270
2047997Ssaidi@eecs.umich.edu#define SCB_Q_UNALIGN		0x0280
2057997Ssaidi@eecs.umich.edu#define SCB_Q_BPT		0x0400
2067997Ssaidi@eecs.umich.edu#define SCB_Q_BUGCHK		0x0410
2077997Ssaidi@eecs.umich.edu#define SCB_Q_OPCDEC		0x0420
2087997Ssaidi@eecs.umich.edu#define SCB_Q_ILLPAL		0x0430
2097997Ssaidi@eecs.umich.edu#define SCB_Q_TRAP		0x0440
2107997Ssaidi@eecs.umich.edu#define SCB_Q_CHMK		0x0480
2117997Ssaidi@eecs.umich.edu#define SCB_Q_CHME		0x0490
2127997Ssaidi@eecs.umich.edu#define SCB_Q_CHMS		0x04A0
2137997Ssaidi@eecs.umich.edu#define SCB_Q_CHMU		0x04B0
2147997Ssaidi@eecs.umich.edu#define SCB_Q_SW0		0x0500
2157997Ssaidi@eecs.umich.edu#define SCB_Q_SW1		0x0510
2167997Ssaidi@eecs.umich.edu#define SCB_Q_SW2		0x0520
2177997Ssaidi@eecs.umich.edu#define SCB_Q_SW3		0x0530
2187997Ssaidi@eecs.umich.edu#define	SCB_Q_SW4		0x0540
2197997Ssaidi@eecs.umich.edu#define SCB_Q_SW5		0x0550
2207997Ssaidi@eecs.umich.edu#define SCB_Q_SW6		0x0560
2217997Ssaidi@eecs.umich.edu#define SCB_Q_SW7		0x0570
2227997Ssaidi@eecs.umich.edu#define SCB_Q_SW8		0x0580
2237997Ssaidi@eecs.umich.edu#define SCB_Q_SW9		0x0590
2247997Ssaidi@eecs.umich.edu#define SCB_Q_SW10		0x05A0
2257997Ssaidi@eecs.umich.edu#define SCB_Q_SW11		0x05B0
2267997Ssaidi@eecs.umich.edu#define SCB_Q_SW12		0x05C0
2277997Ssaidi@eecs.umich.edu#define SCB_Q_SW13		0x05D0
2287997Ssaidi@eecs.umich.edu#define SCB_Q_SW14		0x05E0
2297997Ssaidi@eecs.umich.edu#define SCB_Q_SW15		0x05F0
2307997Ssaidi@eecs.umich.edu#define SCB_Q_CLOCK		0x0600
2317997Ssaidi@eecs.umich.edu#define SCB_Q_INTER		0x0610
2327997Ssaidi@eecs.umich.edu#define SCB_Q_SYSERR        	0x0620
2337997Ssaidi@eecs.umich.edu#define SCB_Q_PROCERR		0x0630
2347997Ssaidi@eecs.umich.edu#define SCB_Q_PWRFAIL		0x0640
2357997Ssaidi@eecs.umich.edu#define SCB_Q_PERFMON		0x0650
2367997Ssaidi@eecs.umich.edu#define SCB_Q_SYSMCHK		0x0660
2377997Ssaidi@eecs.umich.edu#define SCB_Q_PROCMCHK      	0x0670
2387997Ssaidi@eecs.umich.edu#define SCB_Q_PASSREL		0x0680
2397997Ssaidi@eecs.umich.edu
2407997Ssaidi@eecs.umich.edu/*
2417997Ssaidi@eecs.umich.edu**  Stack Frame (FRM) Offsets:
2427997Ssaidi@eecs.umich.edu**
2437997Ssaidi@eecs.umich.edu**  There are two types of system entries for OSF/1 - those for the
2447997Ssaidi@eecs.umich.edu**  callsys CALL_PAL function and those for exceptions and interrupts.
2457997Ssaidi@eecs.umich.edu**  Both entry types use the same stack frame layout.  The stack frame
2467997Ssaidi@eecs.umich.edu**  contains space for the PC, the PS, the saved GP, and the saved
2477997Ssaidi@eecs.umich.edu**  argument registers a0, a1, and a2.  On entry, SP points to the
2487997Ssaidi@eecs.umich.edu**  saved PS.
2497997Ssaidi@eecs.umich.edu*/
2507997Ssaidi@eecs.umich.edu
2517997Ssaidi@eecs.umich.edu#define	FRM_Q_PS	0x0000
2527997Ssaidi@eecs.umich.edu#define FRM_Q_PC	0x0008
2537997Ssaidi@eecs.umich.edu#define FRM_Q_GP	0x0010
2547997Ssaidi@eecs.umich.edu#define FRM_Q_A0	0x0018
2557997Ssaidi@eecs.umich.edu#define FRM_Q_A1	0x0020
2567997Ssaidi@eecs.umich.edu#define FRM_Q_A2	0x0028
2577997Ssaidi@eecs.umich.edu
2587997Ssaidi@eecs.umich.edu#define FRM_K_SIZE	48
2597997Ssaidi@eecs.umich.edu
2607997Ssaidi@eecs.umich.edu#define STACK_FRAME(tmp1,tmp2)	\
2617997Ssaidi@eecs.umich.edu        sll	ps, 63-PS_V_CM, p7;	\
2627997Ssaidi@eecs.umich.edu        bge	p7, 0f;			\
2637997Ssaidi@eecs.umich.edu        bis	zero, zero, ps;		\
2647997Ssaidi@eecs.umich.edu        mtpr	sp, ptUsp;		\
2657997Ssaidi@eecs.umich.edu        mfpr	sp, ptKsp;		\
2667997Ssaidi@eecs.umich.edu0:	lda	sp, 0-FRM_K_SIZE(sp);	\
2677997Ssaidi@eecs.umich.edu        stq	tmp1, FRM_Q_PS(sp);	\
2687997Ssaidi@eecs.umich.edu        stq	tmp2, FRM_Q_PC(sp);	\
2697997Ssaidi@eecs.umich.edu        stq	gp, FRM_Q_GP(sp);	\
2707997Ssaidi@eecs.umich.edu        stq	a0, FRM_Q_A0(sp);	\
2717997Ssaidi@eecs.umich.edu        stq	a1, FRM_Q_A1(sp);	\
2727997Ssaidi@eecs.umich.edu        stq	a2, FRM_Q_A2(sp)
2737997Ssaidi@eecs.umich.edu
2747997Ssaidi@eecs.umich.edu/*
2757997Ssaidi@eecs.umich.edu**  Halt Codes:
2767997Ssaidi@eecs.umich.edu*/
2777997Ssaidi@eecs.umich.edu
2787997Ssaidi@eecs.umich.edu#define HLT_K_RESET	    0x0000
2797997Ssaidi@eecs.umich.edu#define HLT_K_HW_HALT	    0x0001
2807997Ssaidi@eecs.umich.edu#define HLT_K_KSP_INVAL	    0x0002
2817997Ssaidi@eecs.umich.edu#define HLT_K_SCBB_INVAL    0x0003
2827997Ssaidi@eecs.umich.edu#define HLT_K_PTBR_INVAL    0x0004
2837997Ssaidi@eecs.umich.edu#define HLT_K_SW_HALT	    0x0005
2847997Ssaidi@eecs.umich.edu#define HLT_K_DBL_MCHK	    0x0006
2857997Ssaidi@eecs.umich.edu#define HLT_K_MCHK_FROM_PAL 0x0007
2867997Ssaidi@eecs.umich.edu
2877997Ssaidi@eecs.umich.edu/*
2887997Ssaidi@eecs.umich.edu**  Machine Check Codes:
2897997Ssaidi@eecs.umich.edu*/
2907997Ssaidi@eecs.umich.edu
2917997Ssaidi@eecs.umich.edu#define MCHK_K_TPERR	    0x0080
2927997Ssaidi@eecs.umich.edu#define MCHK_K_TCPERR	    0x0082
2937997Ssaidi@eecs.umich.edu#define MCHK_K_HERR	    0x0084
2947997Ssaidi@eecs.umich.edu#define MCHK_K_ECC_C	    0x0086
2957997Ssaidi@eecs.umich.edu#define MCHK_K_ECC_NC	    0x0088
2967997Ssaidi@eecs.umich.edu#define MCHK_K_UNKNOWN	    0x008A
2977997Ssaidi@eecs.umich.edu#define MCHK_K_CACKSOFT	    0x008C
2987997Ssaidi@eecs.umich.edu#define MCHK_K_BUGCHECK	    0x008E
2997997Ssaidi@eecs.umich.edu#define MCHK_K_OS_BUGCHECK  0x0090
3007997Ssaidi@eecs.umich.edu#define MCHK_K_DCPERR	    0x0092
3017997Ssaidi@eecs.umich.edu#define MCHK_K_ICPERR	    0x0094
3027997Ssaidi@eecs.umich.edu#define MCHK_K_RETRY_IRD    0x0096
3037997Ssaidi@eecs.umich.edu#define MCHK_K_PROC_HERR    0x0098
3047997Ssaidi@eecs.umich.edu
3057997Ssaidi@eecs.umich.edu/*
3067997Ssaidi@eecs.umich.edu** System Machine Check Codes:
3077997Ssaidi@eecs.umich.edu*/
3087997Ssaidi@eecs.umich.edu
3097997Ssaidi@eecs.umich.edu#define MCHK_K_READ_NXM     0x0200
3107997Ssaidi@eecs.umich.edu#define MCHK_K_SYS_HERR     0x0202
3117997Ssaidi@eecs.umich.edu
3127997Ssaidi@eecs.umich.edu/*
3137997Ssaidi@eecs.umich.edu**  Machine Check Error Status Summary (MCES) Register Format
3147997Ssaidi@eecs.umich.edu**
3157997Ssaidi@eecs.umich.edu**	 Extent	Size	Name	Function
3167997Ssaidi@eecs.umich.edu**	 ------	----	----	---------------------------------
3177997Ssaidi@eecs.umich.edu**	  <0>	  1	MIP	Machine check in progress
3187997Ssaidi@eecs.umich.edu**	  <1>	  1	SCE	System correctable error in progress
3197997Ssaidi@eecs.umich.edu**	  <2>	  1	PCE	Processor correctable error in progress
3207997Ssaidi@eecs.umich.edu**	  <3>	  1	DPC	Disable PCE error reporting
3217997Ssaidi@eecs.umich.edu**	  <4>	  1	DSC	Disable SCE error reporting
3227997Ssaidi@eecs.umich.edu*/
3237997Ssaidi@eecs.umich.edu
3247997Ssaidi@eecs.umich.edu#define MCES_V_MIP	0
3257997Ssaidi@eecs.umich.edu#define MCES_M_MIP	(1<<MCES_V_MIP)
3267997Ssaidi@eecs.umich.edu#define MCES_V_SCE	1
3277997Ssaidi@eecs.umich.edu#define MCES_M_SCE	(1<<MCES_V_SCE)
3287997Ssaidi@eecs.umich.edu#define MCES_V_PCE	2
3297997Ssaidi@eecs.umich.edu#define MCES_M_PCE	(1<<MCES_V_PCE)
3307997Ssaidi@eecs.umich.edu#define MCES_V_DPC	3
3317997Ssaidi@eecs.umich.edu#define MCES_M_DPC	(1<<MCES_V_DPC)
3327997Ssaidi@eecs.umich.edu#define MCES_V_DSC	4
3337997Ssaidi@eecs.umich.edu#define MCES_M_DSC	(1<<MCES_V_DSC)
3347997Ssaidi@eecs.umich.edu
3357997Ssaidi@eecs.umich.edu#define MCES_M_ALL      (MCES_M_MIP | MCES_M_SCE | MCES_M_PCE | MCES_M_DPC \
3367997Ssaidi@eecs.umich.edu                         | MCES_M_DSC)
3377997Ssaidi@eecs.umich.edu
3387997Ssaidi@eecs.umich.edu/*
3397997Ssaidi@eecs.umich.edu**  Who-Am-I (WHAMI) Register Format
3407997Ssaidi@eecs.umich.edu**
3417997Ssaidi@eecs.umich.edu**	 Extent	Size	Name	Function
3427997Ssaidi@eecs.umich.edu**	 ------	----	----	---------------------------------
3437997Ssaidi@eecs.umich.edu**	  <7:0>	  8	ID	Who-Am-I identifier
3447997Ssaidi@eecs.umich.edu**	  <15:8>   1	SWAP	Swap PALcode flag - character 'S'
3457997Ssaidi@eecs.umich.edu*/
3467997Ssaidi@eecs.umich.edu
3477997Ssaidi@eecs.umich.edu#define WHAMI_V_SWAP	8
3487997Ssaidi@eecs.umich.edu#define WHAMI_M_SWAP	(1<<WHAMI_V_SWAP)
3497997Ssaidi@eecs.umich.edu#define WHAMI_V_ID	0
3507997Ssaidi@eecs.umich.edu#define WHAMI_M_ID	0xFF
3517997Ssaidi@eecs.umich.edu
3527997Ssaidi@eecs.umich.edu#define WHAMI_K_SWAP    0x53    /* Character 'S' */
3537997Ssaidi@eecs.umich.edu
3547997Ssaidi@eecs.umich.edu/*
3557997Ssaidi@eecs.umich.edu**  Conventional Register Usage Definitions
3567997Ssaidi@eecs.umich.edu**
3577997Ssaidi@eecs.umich.edu**  Assembler temporary `at' is `AT' so it doesn't conflict with the
3587997Ssaidi@eecs.umich.edu**  `.set at' assembler directive.
3597997Ssaidi@eecs.umich.edu*/
3607997Ssaidi@eecs.umich.edu
3617997Ssaidi@eecs.umich.edu#define v0		$0	/* Function Return Value Register */
3627997Ssaidi@eecs.umich.edu#define t0		$1	/* Scratch (Temporary) Registers ... */
3637997Ssaidi@eecs.umich.edu#define t1		$2
3647997Ssaidi@eecs.umich.edu#define t2		$3
3657997Ssaidi@eecs.umich.edu#define t3		$4
3667997Ssaidi@eecs.umich.edu#define t4		$5
3677997Ssaidi@eecs.umich.edu#define t5		$6
3687997Ssaidi@eecs.umich.edu#define t6		$7
3697997Ssaidi@eecs.umich.edu#define t7		$8
3707997Ssaidi@eecs.umich.edu#define s0		$9	/* Saved (Non-Volatile) Registers ... */
3717997Ssaidi@eecs.umich.edu#define s1		$10
3727997Ssaidi@eecs.umich.edu#define s2		$11
3737997Ssaidi@eecs.umich.edu#define s3		$12
3747997Ssaidi@eecs.umich.edu#define s4		$13
3757997Ssaidi@eecs.umich.edu#define s5		$14
3767997Ssaidi@eecs.umich.edu#define fp		$15	/* Frame Pointer Register, Or S6 */
3777997Ssaidi@eecs.umich.edu#define s6		$15
3787997Ssaidi@eecs.umich.edu#define a0		$16	/* Argument Registers ... */
3797997Ssaidi@eecs.umich.edu#define a1		$17
3807997Ssaidi@eecs.umich.edu#define a2		$18
3817997Ssaidi@eecs.umich.edu#define a3		$19
3827997Ssaidi@eecs.umich.edu#define a4		$20
3837997Ssaidi@eecs.umich.edu#define a5		$21
3847997Ssaidi@eecs.umich.edu#define t8		$22	/* Scratch (Temporary) Registers ... */
3857997Ssaidi@eecs.umich.edu#define t9		$23
3867997Ssaidi@eecs.umich.edu#define t10		$24
3877997Ssaidi@eecs.umich.edu#define t11		$25
3887997Ssaidi@eecs.umich.edu#define ra		$26	/* Return Address Register */
3897997Ssaidi@eecs.umich.edu#define pv		$27	/* Procedure Value Register, Or T12 */
3907997Ssaidi@eecs.umich.edu#define t12		$27
3917997Ssaidi@eecs.umich.edu#define AT		$28	/* Assembler Temporary (Volatile) Register */
3927997Ssaidi@eecs.umich.edu#define gp		$29	/* Global Pointer Register */
3937997Ssaidi@eecs.umich.edu#define sp		$30	/* Stack Pointer Register */
3947997Ssaidi@eecs.umich.edu#define zero		$31	/* Zero Register */
3957997Ssaidi@eecs.umich.edu
3967997Ssaidi@eecs.umich.edu/*
3977997Ssaidi@eecs.umich.edu**  OSF/1 Unprivileged CALL_PAL Entry Offsets:
3987997Ssaidi@eecs.umich.edu**
3997997Ssaidi@eecs.umich.edu**	Entry Name	    Offset (Hex)
4007997Ssaidi@eecs.umich.edu**
4017997Ssaidi@eecs.umich.edu**	bpt		     0080
4027997Ssaidi@eecs.umich.edu**	bugchk		     0081
4037997Ssaidi@eecs.umich.edu**	callsys		     0083
4047997Ssaidi@eecs.umich.edu**	imb		     0086
4057997Ssaidi@eecs.umich.edu**	rdunique	     009E
4067997Ssaidi@eecs.umich.edu**	wrunique	     009F
4077997Ssaidi@eecs.umich.edu**	gentrap		     00AA
4087997Ssaidi@eecs.umich.edu**	dbgstop		     00AD
4097997Ssaidi@eecs.umich.edu*/
4107997Ssaidi@eecs.umich.edu
4117997Ssaidi@eecs.umich.edu#define UNPRIV			    0x80
4127997Ssaidi@eecs.umich.edu#define	PAL_BPT_ENTRY		    0x80
4137997Ssaidi@eecs.umich.edu#define PAL_BUGCHK_ENTRY	    0x81
4147997Ssaidi@eecs.umich.edu#define PAL_CALLSYS_ENTRY	    0x83
4157997Ssaidi@eecs.umich.edu#define PAL_IMB_ENTRY		    0x86
4167997Ssaidi@eecs.umich.edu#define PAL_RDUNIQUE_ENTRY	    0x9E
4177997Ssaidi@eecs.umich.edu#define PAL_WRUNIQUE_ENTRY	    0x9F
4187997Ssaidi@eecs.umich.edu#define PAL_GENTRAP_ENTRY	    0xAA
4197997Ssaidi@eecs.umich.edu
4207997Ssaidi@eecs.umich.edu#if defined(KDEBUG)
4217997Ssaidi@eecs.umich.edu#define	PAL_DBGSTOP_ENTRY	    0xAD
4227997Ssaidi@eecs.umich.edu/* #define NUM_UNPRIV_CALL_PALS	    10 */
4237997Ssaidi@eecs.umich.edu#else
4247997Ssaidi@eecs.umich.edu/* #define NUM_UNPRIV_CALL_PALS	    9  */
4257997Ssaidi@eecs.umich.edu#endif /* KDEBUG */
4267997Ssaidi@eecs.umich.edu
4277997Ssaidi@eecs.umich.edu/*
4287997Ssaidi@eecs.umich.edu**  OSF/1 Privileged CALL_PAL Entry Offsets:
4297997Ssaidi@eecs.umich.edu**
4307997Ssaidi@eecs.umich.edu**	Entry Name	    Offset (Hex)
4317997Ssaidi@eecs.umich.edu**
4327997Ssaidi@eecs.umich.edu**	halt		     0000
4337997Ssaidi@eecs.umich.edu**	cflush		     0001
4347997Ssaidi@eecs.umich.edu**	draina		     0002
4357997Ssaidi@eecs.umich.edu**	cserve		     0009
4367997Ssaidi@eecs.umich.edu**	swppal		     000A
4377997Ssaidi@eecs.umich.edu**	rdmces		     0010
4387997Ssaidi@eecs.umich.edu**	wrmces		     0011
4397997Ssaidi@eecs.umich.edu**	wrfen		     002B
4407997Ssaidi@eecs.umich.edu**	wrvptptr	     002D
4417997Ssaidi@eecs.umich.edu**	swpctx		     0030
4427997Ssaidi@eecs.umich.edu**	wrval		     0031
4437997Ssaidi@eecs.umich.edu**	rdval		     0032
4447997Ssaidi@eecs.umich.edu**	tbi		     0033
4457997Ssaidi@eecs.umich.edu**	wrent		     0034
4467997Ssaidi@eecs.umich.edu**	swpipl		     0035
4477997Ssaidi@eecs.umich.edu**	rdps		     0036
4487997Ssaidi@eecs.umich.edu**	wrkgp		     0037
4497997Ssaidi@eecs.umich.edu**	wrusp		     0038
4507997Ssaidi@eecs.umich.edu**	rdusp		     003A
4517997Ssaidi@eecs.umich.edu**	whami		     003C
4527997Ssaidi@eecs.umich.edu**	retsys		     003D
4537997Ssaidi@eecs.umich.edu**	rti		     003F
4547997Ssaidi@eecs.umich.edu*/
4557997Ssaidi@eecs.umich.edu
4567997Ssaidi@eecs.umich.edu#define PAL_HALT_ENTRY	    0x0000
4577997Ssaidi@eecs.umich.edu#define PAL_CFLUSH_ENTRY    0x0001
4587997Ssaidi@eecs.umich.edu#define PAL_DRAINA_ENTRY    0x0002
4597997Ssaidi@eecs.umich.edu#define PAL_CSERVE_ENTRY    0x0009
4607997Ssaidi@eecs.umich.edu#define PAL_SWPPAL_ENTRY    0x000A
4617997Ssaidi@eecs.umich.edu#define PAL_WRIPIR_ENTRY    0x000D
4627997Ssaidi@eecs.umich.edu#define PAL_RDMCES_ENTRY    0x0010
4637997Ssaidi@eecs.umich.edu#define PAL_WRMCES_ENTRY    0x0011
4647997Ssaidi@eecs.umich.edu#define PAL_WRFEN_ENTRY	    0x002B
4657997Ssaidi@eecs.umich.edu#define PAL_WRVPTPTR_ENTRY  0x002D
4667997Ssaidi@eecs.umich.edu#define PAL_SWPCTX_ENTRY    0x0030
4677997Ssaidi@eecs.umich.edu#define PAL_WRVAL_ENTRY	    0x0031
4687997Ssaidi@eecs.umich.edu#define PAL_RDVAL_ENTRY	    0x0032
4697997Ssaidi@eecs.umich.edu#define PAL_TBI_ENTRY	    0x0033
4707997Ssaidi@eecs.umich.edu#define PAL_WRENT_ENTRY	    0x0034
4717997Ssaidi@eecs.umich.edu#define PAL_SWPIPL_ENTRY    0x0035
4727997Ssaidi@eecs.umich.edu#define PAL_RDPS_ENTRY	    0x0036
4737997Ssaidi@eecs.umich.edu#define PAL_WRKGP_ENTRY	    0x0037
4747997Ssaidi@eecs.umich.edu#define PAL_WRUSP_ENTRY	    0x0038
4757997Ssaidi@eecs.umich.edu#define PAL_RDUSP_ENTRY	    0x003A
4767997Ssaidi@eecs.umich.edu#define PAL_WHAMI_ENTRY	    0x003C
4777997Ssaidi@eecs.umich.edu#define PAL_RETSYS_ENTRY    0x003D
4787997Ssaidi@eecs.umich.edu#define PAL_RTI_ENTRY	    0x003F
4797997Ssaidi@eecs.umich.edu
4807997Ssaidi@eecs.umich.edu#define NUM_PRIV_CALL_PALS  23
4817997Ssaidi@eecs.umich.edu
4827997Ssaidi@eecs.umich.edu#endif
4837997Ssaidi@eecs.umich.edu
484