Searched refs:write_misses (Results 1 - 10 of 10) sorted by relevance

/gem5/ext/mcpat/
H A Dcacheunit.h120 // read_misses and write_misses are still required for this method for
132 double write_misses; member in class:CacheStatistics
H A Dcacheunit.cc167 cache_stats.read_accesses + cache_stats.write_misses;
173 cache_stats.read_misses + cache_stats.write_misses;
269 cache_stats.read_misses + cache_stats.write_misses;
271 cache_stats.read_misses + cache_stats.write_misses;
324 cache_stats.read_misses + cache_stats.write_misses;
326 cache_stats.read_misses + cache_stats.write_misses;
437 arrayPtr->rtp_stats.readAc.access = cache_stats.write_misses;
438 arrayPtr->rtp_stats.writeAc.access = cache_stats.write_misses;
614 ASSIGN_FP_IF("write_misses", cache_stats.write_misses);
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/gem5/src/arch/mips/
H A Dtlb.hh75 mutable Stats::Scalar write_misses; member in class:MipsISA::TLB
H A Dtlb.cc253 write_misses
254 .name(name() + ".write_misses")
280 misses = read_misses + write_misses;
/gem5/src/arch/riscv/
H A Dtlb.hh74 mutable Stats::Scalar write_misses; member in class:RiscvISA::TLB
H A Dtlb.cc255 write_misses
256 .name(name() + ".write_misses")
282 misses = read_misses + write_misses;
/gem5/src/arch/alpha/
H A Dtlb.hh65 mutable Stats::Scalar write_misses; member in class:AlphaISA::TLB
H A Dtlb.cc121 write_misses
122 .name(name() + ".write_misses")
157 data_misses = read_misses + write_misses;
524 if (write) { write_misses++; } else { read_misses++; }
/gem5/src/arch/power/
H A Dtlb.hh124 mutable Stats::Scalar write_misses; member in class:PowerISA::TLB
H A Dtlb.cc250 write_misses
251 .name(name() + ".write_misses")
277 misses = read_misses + write_misses;

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