1/*****************************************************************************
2 *                                McPAT
3 *                      SOFTWARE LICENSE AGREEMENT
4 *            Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
5 *                          All Rights Reserved
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met: redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer;
11 * redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution;
14 * neither the name of the copyright holders nor the names of its
15 * contributors may be used to endorse or promote products derived from
16 * this software without specific prior written permission.
17
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
24 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Authors: Joel Hestness
31 *          Yasuko Eckert
32 *
33 ***************************************************************************/
34
35#ifndef CACHEUNIT_H_
36#define CACHEUNIT_H_
37
38#include "area.h"
39#include "array.h"
40#include "basic_components.h"
41#include "logic.h"
42#include "parameter.h"
43
44class CacheParameters {
45public:
46    enum Dir_type dir_ty;
47    double clockRate;
48    double capacity;
49    double blockW;
50    double assoc;
51    double nbanks;
52    double throughput;
53    double latency;
54    int missb_size;
55    int fu_size;
56    int prefetchb_size;
57    int wbb_size;
58    int missb_assoc;
59    int fu_assoc;
60    int prefetchb_assoc;
61    int wbb_assoc;
62    int missb_banks;
63    int fu_banks;
64    int prefetchb_banks;
65    int wbb_banks;
66    enum Access_mode cache_access_mode;
67    enum Access_mode miss_buff_access_mode;
68    enum Access_mode fetch_buff_access_mode;
69    enum Access_mode prefetch_buff_access_mode;
70    enum Access_mode writeback_buff_access_mode;
71    int cache_rw_ports;
72    int cache_rd_ports;
73    int cache_wr_ports;
74    int cache_se_rd_ports;
75    int cache_search_ports;
76    int miss_buff_rw_ports;
77    int miss_buff_rd_ports;
78    int miss_buff_wr_ports;
79    int miss_buff_se_rd_ports;
80    int miss_buff_search_ports;
81    int fetch_buff_rw_ports;
82    int fetch_buff_rd_ports;
83    int fetch_buff_wr_ports;
84    int fetch_buff_se_rd_ports;
85    int fetch_buff_search_ports;
86    int pf_buff_rw_ports;
87    int pf_buff_rd_ports;
88    int pf_buff_wr_ports;
89    int pf_buff_se_rd_ports;
90    int pf_buff_search_ports;
91    int wb_buff_rw_ports;
92    int wb_buff_rd_ports;
93    int wb_buff_wr_ports;
94    int wb_buff_se_rd_ports;
95    int wb_buff_search_ports;
96    bool pure_ram;
97    enum CacheLevel cache_level;
98    enum Device_ty device_ty;
99    enum Core_type core_ty;
100    int num_cores;
101};
102
103class CacheStatistics {
104public:
105    // Duty cycle is used for estimating TDP. It should reflect the highest
106    // sustainable rate of access to the cache unit in execution of a benchmark
107    // Default should be 1.0: one access per cycle
108    double duty_cycle;
109    // This duty cycle is only used for SBT directory types
110    double dir_duty_cycle;
111    // The following two stats are also used for estimating TDP.
112    double tdp_read_access_scalar;
113    double tdp_write_access_scalar;
114    // There are 2 ways to calculate dynamic power from activity statistics:
115    // Default is false
116    bool use_detailed_stats;
117    // 1) Count the number and type of accesses to each cache array
118    //    splitting data and tag arrays (use_detailed_stats = true).
119    //    These are extremely detailed statistics.
120    //    read_misses and write_misses are still required for this method for
121    //    various buffers associated with this cache.
122    double num_data_array_reads;
123    double num_data_array_writes;
124    double num_tag_array_reads;
125    double num_tag_array_writes;
126    // 2) Count the number and type of access to the cache unit and
127    //    use them to extrapolate the number of accesses to the other
128    //    subcomponents (cache arrays and buffers)
129    double read_accesses;
130    double write_accesses;
131    double read_misses;
132    double write_misses;
133    double conflicts;
134    // The following is only used for SBT directory types
135    int homenode_read_accesses;
136    int homenode_write_accesses;
137    int homenode_read_misses;
138    int homenode_write_misses;
139    double homenode_access_scalar;
140    double tdp_sbt_write_access_scalar;
141};
142
143class CacheUnit : public McPATComponent {
144public:
145    static bool is_cache;
146    static bool pure_cam;
147    // This is used for CacheArray objects
148    static bool opt_local;
149    static bool force_cache_config;
150
151    int ithCache;
152    CacheParameters cache_params;
153    CacheStatistics cache_stats;
154    Cache_type cacheType;
155    bool calculate_runtime_data_and_tag;
156    double dir_overhead;
157
158    double scktRatio;
159
160    // TODO: REMOVE _interface_ip... It promotes a mess. Find a better way...
161    CacheUnit(XMLNode* _xml_data, InputParameter* _interface_ip);
162    void set_cache_param_from_xml_data();
163    void computeEnergy();
164    ~CacheUnit() {};
165};
166
167#endif /* CACHEUNIT_H_ */
168