Searched refs:store (Results 1 - 22 of 22) sorted by relevance

/gem5/src/arch/sparc/insts/
H A Dmem.cc43 bool store = flags[IsStore]; local
46 if (store) {
51 if (_srcRegIdx[!store ? 0 : 1].index() != 0) {
52 printSrcReg(response, !store ? 0 : 1);
55 printSrcReg(response, !store ? 1 : 2);
/gem5/src/arch/mips/
H A Dfaults.hh194 bool store; member in class:MipsISA::AddressFault
196 AddressFault(Addr _vaddr, bool _store) : vaddr(_vaddr), store(_store)
219 return store ? ExcCodeAdES : ExcCodeAdEL;
269 return this->store ? ExcCodeTlbS : ExcCodeTlbL;
276 TlbRefillFault(Addr asid, Addr vaddr, Addr vpn, bool store) : argument
277 TlbFault<TlbRefillFault>(asid, vaddr, vpn, store)
291 TlbInvalidFault(Addr asid, Addr vaddr, Addr vpn, bool store) : argument
292 TlbFault<TlbInvalidFault>(asid, vaddr, vpn, store)
/gem5/src/mem/ruby/profiler/
H A DStoreTrace.hh45 void store(NodeID node);
56 static int64_t s_total_samples; // Total number of store lifetimes
69 int64_t m_total_samples; // Total number of store lifetimes of this line
H A DStoreTrace.cc35 bool StoreTrace::s_init = false; // Total number of store lifetimes of
37 int64_t StoreTrace::s_total_samples = 0; // Total number of store
107 StoreTrace::store(NodeID node) function in class:StoreTrace
/gem5/src/mem/ruby/system/
H A DRubySystem.py49 store and only use ruby for timing.")
/gem5/src/dev/arm/
H A Dsmmu_v3_caches.hh131 void store(const Entry &incoming, AllocPolicy alloc);
178 void store(const Entry &incoming);
219 void store(const Entry &incoming);
267 void store(const Entry &incoming);
311 void store(const Entry &incoming);
H A Dsmmu_v3_caches.cc240 SMMUTLB::store(const Entry &incoming, AllocPolicy alloc) function in class:SMMUTLB
243 panic("Tried to store an invalid entry\n");
492 ARMArchTLB::store(const Entry &incoming) function in class:ARMArchTLB
495 panic("Tried to store an invalid entry\n");
691 IPACache::store(const Entry &incoming) function in class:IPACache
694 panic("Tried to store an invalid entry\n");
870 ConfigCache::store(const Entry &incoming) function in class:ConfigCache
873 panic("Tried to store an invalid entry\n");
1057 WalkCache::store(const Entry &incoming) function in class:WalkCache
1060 panic("Tried to store a
[all...]
H A Dsmmu_v3_transl.cc433 ifc.microTLB->store(e, SMMUTLB::ALLOC_ANY_WAY);
470 ifc.mainTLB->store(e, alloc);
499 smmu.tlb.store(e);
571 smmu.configCache.store(e);
717 smmu.walkCache.store(e);
1016 smmu.ipaCache.store(e);
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/
H A Ddirty.S28 # Try a faulting store to make sure dirty bit is not set
42 # Try a non-faulting store to make sure dirty bit is set
/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/
H A Dma_addr.S57 # indicate it's a store test
60 /* Check that a misaligned store has some effect and takes no exception,
/gem5/tests/test-progs/insttest/src/riscv/
H A Drv64i.cpp124 expect<uint8_t>(0xFF, []{return I::store<int8_t>(-1);}, "sb");
125 expect<uint16_t>(0xFFFF, []{return I::store<int16_t>(-1);}, "sh");
126 expect<uint32_t>(0xFFFFFFFF, []{return I::store<int32_t>(-1);}, "sw");
358 expect<uint64_t>(-1, []{return I::store<int64_t>(-1);}, "sd");
H A Drv64d.h76 store(double fs) function in namespace:D
H A Drv64f.h76 store(float fs) function in namespace:F
H A Drv64i.h195 store(const M& rs2) function in namespace:I
H A Drv64f.cpp50 expect<float>(1.816, []{return F::store(1.816);}, "fsw");
H A Drv64d.cpp45 expect<double>(1.61803398875, []{return D::store(1.61803398875);}, "fsd");
/gem5/ext/systemc/src/sysc/qt/md/
H A Dhppa_b.s53 stwm %r3,64(%sp) ; store r3 (may be used by caller)
H A Dksr1.s286 finop ; st8 %c14,488(%sp) # store ret addr
352 # Pop the frame used to store the thread's initial data
/gem5/src/cpu/o3/
H A Dinst_queue.hh260 /** Indicates an ordering violation between a store and a load. */
261 void violation(const DynInstPtr &store, const DynInstPtr &faulting_load);
H A Dinst_queue_impl.hh1199 InstructionQueue<Impl>::violation(const DynInstPtr &store, argument
1203 memDepUnit[store->threadNumber].violation(store, faulting_load);
/gem5/src/cpu/minor/
H A Dlsq.cc255 DPRINTF(MinorMem, "Moving %s barrier out of store buffer inst: %s\n",
722 /* @todo, support store amalgamation */
744 warn("%s: store buffer insertion without space to insert from"
748 DPRINTF(MinorMem, "Pushing store: %s into store buffer\n", request);
758 * the store buffer */
770 /* Traverse the store buffer in reverse order (most to least recent)
775 /* Cache maintenance instructions go down via the store path but
811 LSQRequestPtr store = slots[slot_number]; local
813 assert(store
[all...]
/gem5/ext/systemc/src/sysc/datatypes/int/
H A Dsc_nbcommon.inc2733 // will be used as a temporary store. The following code tries to
2881 // will be used as a temporary store. The following code tries to

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