Searched refs:slave (Results 1 - 25 of 92) sorted by relevance

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/gem5/src/arch/generic/
H A DBaseTLB.py39 slave = VectorSlavePort("Port closer to the CPU side") variable in class:BaseTLB
/gem5/configs/ruby/
H A DMOESI_CMP_directory.py132 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
134 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
136 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
138 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
177 l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
179 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
181 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
184 l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master
186 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master
188 l2_cntrl.responseToL2Cache.slave
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H A DMOESI_CMP_token.py135 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
137 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
139 l1_cntrl.persistentFromL1Cache.master = ruby_system.network.slave
143 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
145 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
147 l1_cntrl.persistentToL1Cache.slave = ruby_system.network.master
171 l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave
173 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
175 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
178 l2_cntrl.GlobalRequestToL2Cache.slave
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H A DMESI_Two_Level.py122 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave
124 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave
126 l1_cntrl.unblockFromL1Cache.master = ruby_system.network.slave
131 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master
133 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master
156 l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave
158 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
160 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
163 l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master
165 l2_cntrl.L1RequestToL2Cache.slave
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H A DMESI_Three_Level.py156 l1_cntrl.requestToL2.master = ruby_system.network.slave
158 l1_cntrl.responseToL2.master = ruby_system.network.slave
160 l1_cntrl.unblockToL2.master = ruby_system.network.slave
163 l1_cntrl.requestFromL2.slave = ruby_system.network.master
165 l1_cntrl.responseFromL2.slave = ruby_system.network.master
185 l2_cntrl.DirRequestFromL2Cache.master = ruby_system.network.slave
187 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave
189 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave
192 l2_cntrl.unblockToL2Cache.slave = ruby_system.network.master
194 l2_cntrl.L1RequestToL2Cache.slave
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H A DMOESI_hammer.py131 l1_cntrl.requestFromCache.master = ruby_system.network.slave
133 l1_cntrl.responseFromCache.master = ruby_system.network.slave
135 l1_cntrl.unblockFromCache.master = ruby_system.network.slave
142 l1_cntrl.forwardToCache.slave = ruby_system.network.master
144 l1_cntrl.responseToCache.slave = ruby_system.network.master
195 dir_cntrl.forwardFromDir.master = ruby_system.network.slave
197 dir_cntrl.responseFromDir.master = ruby_system.network.slave
199 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
204 dir_cntrl.unblockToDir.slave = ruby_system.network.master
206 dir_cntrl.responseToDir.slave
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H A DMI_example.py110 l1_cntrl.requestFromCache.master = ruby_system.network.slave
112 l1_cntrl.responseFromCache.master = ruby_system.network.slave
114 l1_cntrl.forwardToCache.slave = ruby_system.network.master
116 l1_cntrl.responseToCache.slave = ruby_system.network.master
137 dir_cntrl.requestToDir.slave = ruby_system.network.master
139 dir_cntrl.dmaRequestToDir.slave = ruby_system.network.master
142 dir_cntrl.responseFromDir.master = ruby_system.network.slave
144 dir_cntrl.dmaResponseFromDir.master = ruby_system.network.slave
146 dir_cntrl.forwardFromDir.master = ruby_system.network.slave
163 exec("ruby_system.dma_cntrl%d.dma_sequencer.slave
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/gem5/tests/configs/
H A Dtgen-simple-mem.py65 system.cpu.port = system.monitor.slave
66 system.monitor.master = system.membus.slave
69 system.system_port = system.membus.slave
H A Dtgen-dram-ctrl.py62 system.cpu.port = system.monitor.slave
63 system.monitor.master = system.membus.slave
66 system.system_port = system.membus.slave
H A Dpc-simple-timing-ruby.py77 system.iobus.master = system.ruby._io_port.slave
83 cpu.icache_port = system.ruby._cpu_ports[i].slave
84 cpu.dcache_port = system.ruby._cpu_ports[i].slave
85 cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
86 cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
89 cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
/gem5/configs/example/
H A Dhmctest.py54 # use timing mode for the interaction between master-slave ports
68 system.tgen[i].port = system.membus.slave
70 system.system_port = system.membus.slave
73 system.tgen[i].port = system.membus.slave
76 system.tgen[2].port = hh.lmonitor[2].slave
77 hh.lmonitor[2].master = hh.seriallink[2].slave
78 system.tgen[3].port = hh.lmonitor[3].slave
79 hh.lmonitor[3].master = hh.seriallink[3].slave
81 system.tgen[2].port = hh.seriallink[2].slave
82 system.tgen[3].port = hh.seriallink[3].slave
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/gem5/src/mem/
H A DBridge.py48 slave = SlavePort('Slave port') variable in class:Bridge
H A DAddrMapper.py42 # slave port side of the mapper to the master port side. When the
43 # slave port is queried for the address ranges, it also performs the
45 # the master port (i.e. the memory side) to the slave port are
54 slave = SlavePort("Slave port") variable in class:AddrMapper
H A DMemDelay.py47 slave = SlavePort("Slave port") variable in class:MemDelay
H A DMemChecker.py52 slave = SlavePort("Slave port") variable in class:MemCheckerMonitor
53 cpu_side = SlavePort("Alias for slave")
/gem5/src/dev/x86/
H A DI8259.py47 slave = Param.I8259(NULL, 'Slave I8259, if any') variable in class:I8259
/gem5/configs/common/
H A DHMC.py365 mb.master = hh.lmonitor[i].slave
366 hh.lmonitor[i].master = hh.seriallink[i].slave
368 mb.master = hh.seriallink[i].slave
372 mb.master = hh.lmonitor[0].slave
373 hh.lmonitor[0].master = hh.seriallink[0].slave
374 mb.master = hh.lmonitor[1].slave
375 hh.lmonitor[1].master = hh.seriallink[1].slave
377 mb.master = hh.seriallink[0].slave
378 mb.master = hh.seriallink[1].slave
383 hh.lmonitor[i].master = hh.seriallink[i].slave
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/gem5/configs/learning_gem5/part3/
H A Druby_caches_MI_example.py104 system.system_port = self.sys_port_proxy.slave
108 cpu.icache_port = self.sequencers[i].slave
109 cpu.dcache_port = self.sequencers[i].slave
113 cpu.interrupts[0].int_master = self.sequencers[i].slave
116 cpu.itb.walker.port = self.sequencers[i].slave
117 cpu.dtb.walker.port = self.sequencers[i].slave
166 self.requestFromCache.master = ruby_system.network.slave
168 self.responseFromCache.master = ruby_system.network.slave
170 self.forwardToCache.slave = ruby_system.network.master
172 self.responseToCache.slave
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H A Dmsi_caches.py106 system.system_port = self.sys_port_proxy.slave
110 cpu.icache_port = self.sequencers[i].slave
111 cpu.dcache_port = self.sequencers[i].slave
115 cpu.interrupts[0].int_master = self.sequencers[i].slave
118 cpu.itb.walker.port = self.sequencers[i].slave
119 cpu.dtb.walker.port = self.sequencers[i].slave
173 # Ruby network. In this case, "slave/master" don't mean the same thing
175 # then you use the "master", otherwise, the slave.
177 self.requestToDir.master = ruby_system.network.slave
179 self.responseToDirOrSibling.master = ruby_system.network.slave
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H A Dtest_caches.py98 system.system_port = self.sys_port_proxy.slave
103 tester.cpuInstDataPort = seq.slave
105 tester.cpuDataPort = seq.slave
107 tester.cpuInstDataPort = seq.slave
/gem5/util/tlm/conf/
H A Dtlm_master.py67 system.system_port = system.membus.slave
69 system.tlm.port = system.membus.slave
H A Dtlm_slave.py70 system.cpu.port = system.membus.slave
71 system.system_port = system.membus.slave
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py122 system.system_port = system.membus.slave
123 system.cpu.icache.mem_side = system.tol2bus.slave
124 system.cpu.dcache.mem_side = system.tol2bus.slave
126 system.l2cache.mem_side = system.membus.slave
/gem5/src/mem/ruby/network/
H A DMessageBuffer.py46 slave = SlavePort("Slave port from MessageBuffer sender") variable in class:MessageBuffer
/gem5/configs/learning_gem5/part1/
H A Dsimple.py68 system.cpu.icache_port = system.membus.slave
69 system.cpu.dcache_port = system.membus.slave
78 system.cpu.interrupts[0].int_master = system.membus.slave
87 system.system_port = system.membus.slave

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