| /gem5/src/gpu-compute/ |
| H A D | fetch_stage.cc | 88 uint32_t simdId = wavefront->simdId; local
89 fetchUnit[simdId].processFetchReturn(pkt);
95 fetchUnit[wavefront->simdId].fetch(pkt, wavefront);
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| H A D | schedule_stage.cc | 90 if (waveToMemPipe->simdId == waveToExePipe->simdId) {
91 int simdId = waveToMemPipe->simdId; local
101 if (computeUnit->vrf[simdId]->
108 waveStatusList[simdId]->at(waveToExePipe->wfSlotId)
139 waveStatusList[waveToBeDispatched->simdId]->at(
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| H A D | wavefront.cc | 55 simdId = p->simdId;
299 return physicalVgprIndex % computeUnit->vrf[simdId]->numRegs();
360 computeUnit->cu_id, simdId, wfSlotId, ii->disassemble());
364 if (!computeUnit->wfWait[simdId].prerdy()) {
377 if (!computeUnit->wfWait[simdId].prerdy()) {
385 if (!computeUnit->wfWait[simdId].prerdy()) {
401 if (!computeUnit->wfWait[simdId].prerdy()) {
405 if (!computeUnit->vrf[simdId]->vrfOperandAccessReady(this, ii,
410 if (!computeUnit->vrf[simdId]
[all...] |
| H A D | condition_register_state.cc | 77 registerEvent(w->simdId, ii->getRegisterIndex(i, ii),
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| H A D | fetch_unit.cc | 133 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId, vaddr);
214 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId,
242 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId,
246 computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId,
265 wavefront->simdId, wavefront->wfSlotId, pkt->req->getPaddr(),
296 computeUnit->cu_id, wavefront->simdId,
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| H A D | compute_unit.cc | 306 "WF[%d][%d]\n", _n_wave, barrier_id, cu_id, w->simdId, w->wfSlotId);
486 ComputeUnit::cedeSIMD(int simdId, int wfSlotId) argument
507 if (cur_wave.simdId == simdId &&
514 if (owner_wave.simdId != cur_wave.simdId ||
633 computeUnit->wfList[gpuDynInst->simdId][gpuDynInst->wfSlotId];
638 computeUnit->cu_id, w->simdId, w->wfSlotId,
648 computeUnit->cu_id, gpuDynInst->simdId,
676 computeUnit->cu_id, gpuDynInst->simdId, gpuDynIns
1133 int simdId = gpuDynInst->simdId; local
[all...] |
| H A D | vector_register_file.cc | 52 simdId(p->simd_id), numRegsPerSimd(p->num_regs_per_simd),
56 fatal_if(simdId < 0, "Illegal SIMD id for VRF");
184 computeUnit->registerEvent(w->simdId, physReg,
206 computeUnit->registerEvent(w->simdId, regVec[i], operandSize,
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| H A D | global_memory_pipeline.cc | 77 w->computeUnit->vrf[w->simdId]->
149 computeUnit->cu_id, mp->simdId, mp->wfSlotId);
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| H A D | local_memory_pipeline.cc | 71 w->computeUnit->vrf[w->simdId]->
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| H A D | vector_register_file.hh | 132 int simdId; member in class:VrfAccessType::VectorRegisterFile
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| H A D | compute_unit.hh | 222 registerEvent(uint32_t simdId, argument
227 regIdxVec.push_back(std::make_pair(simdId, regIdx));
231 regIdxVec.push_back(std::make_pair(simdId,
280 bool cedeSIMD(int simdId, int wfSlotId);
729 : simdId(_simdId), wfSlotId(_wfSlotId) { }
731 int simdId; member in class:ComputeUnit::waveIdentifier
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| H A D | GPU.py | 70 simdId = Param.Int('SIMD id (0-ComputeUnit.num_SIMDs)') variable in class:Wavefront
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| H A D | gpu_dyn_inst.cc | 158 cu->cu_id, simdId, wfSlotId, exec_mask);
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| H A D | wavefront.hh | 165 int simdId; member in class:Wavefront
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| H A D | gpu_dyn_inst.hh | 248 int simdId; member in class:GPUDynInst
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| /gem5/src/arch/hsail/insts/ |
| H A D | main.cc | 162 w->computeUnit->vectorRegsReserved[w->simdId] -=
165 assert(w->computeUnit->vectorRegsReserved[w->simdId] >= 0);
169 w->computeUnit->vrf[w->simdId]->numRegs();
171 w->computeUnit->vrf[w->simdId]->manager->
179 w->computeUnit->cu_id, w->simdId, w->wfSlotId, w->wfDynId);
190 local_mempacket->simdId = w->simdId;
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| H A D | pseudo_inst.cc | 191 disassemble(), w->computeUnit->cu_id, w->simdId,
195 disassemble(), w->computeUnit->cu_id, w->simdId,
214 disassemble(), w->computeUnit->cu_id, w->simdId,
218 disassemble(), w->computeUnit->cu_id, w->simdId,
429 res_str += csprintf(" Phase ID: %i\n", w->simdId);
644 m->simdId = w->simdId;
684 m->simdId = w->simdId;
723 m->simdId
[all...] |
| H A D | mem_impl.hh | 234 m->simdId = w->simdId;
413 m->simdId = w->simdId;
582 m->simdId = w->simdId;
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| H A D | mem.hh | 551 "ld inst)\n", w->computeUnit->cu_id, w->simdId,
556 w->computeUnit->vrf[w->simdId]->write<c0>(physVgpr,
567 vrf[w->simdId]->exec(gpuDynInst->seqNum(), w, regVec,
1531 "ld inst)\n", w->computeUnit->cu_id, w->simdId,
1536 w->computeUnit->vrf[w->simdId]->write<CType>(physVgpr, *p1, i);
1545 vrf[w->simdId]->exec(gpuDynInst->seqNum(), w, regVec,
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| H A D | decl.hh | 1129 gpuDynInst->simdId = w->simdId;
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| /gem5/src/arch/hsail/ |
| H A D | operand.hh | 167 ret = (w->computeUnit->vrf[w->simdId]->
172 ret = (w->computeUnit->vrf[w->simdId]->
177 ret = w->computeUnit->vrf[w->simdId]->
205 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, val);
210 w->computeUnit->vrf[w->simdId]->write<OperandType>(vgprIdx,val,lane);
218 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx, val);
222 w->computeUnit->vrf[w->simdId]->write<uint32_t>(vgprIdx, val, lane);
268 return w->computeUnit->vrf[w->simdId]->read<OperandType>(vgprIdx,lane);
276 w->computeUnit->cu_id, w->simdId, w->wfSlotId, lane, regIdx,
283 w->computeUnit->vrf[w->simdId]
[all...] |
| /gem5/tests/configs/ |
| H A D | gpu-ruby.py | 232 wavefronts.append(Wavefront(simdId = j, wf_slot_id = k))
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| /gem5/configs/example/ |
| H A D | apu_se.py | 261 wavefronts.append(Wavefront(simdId = j, wf_slot_id = k,
|