Searched refs:readMiscReg (Results 1 - 25 of 66) sorted by relevance

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/gem5/src/arch/arm/
H A Disa_device.hh83 virtual RegVal readMiscReg(int misc_reg) = 0;
104 RegVal readMiscReg(int misc_reg) override;
H A Disa_device.cc69 DummyISADevice::readMiscReg(int misc_reg) function in class:ArmISA::DummyISADevice
H A Dlocked_mem.hh72 xc->readMiscReg(MISCREG_LOCKFLAG));
73 if (!xc->readMiscReg(MISCREG_LOCKFLAG))
76 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
107 xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR));
123 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
124 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
H A Dutility.cc198 SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) :
199 tc->readMiscReg(MISCREG_SCR);
201 scr, tc->readMiscReg(MISCREG_CPSR));
207 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
214 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
221 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR);
242 return tc->readMiscReg(MISCREG_VMPIDR_EL2);
304 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
329 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
332 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL
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H A Dinterrupts.cc57 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
60 hcr = tc->readMiscReg(MISCREG_HCR);
65 scr = tc->readMiscReg(MISCREG_SCR);
67 scr = tc->readMiscReg(MISCREG_SCR_EL3);
H A Disa.cc452 ISA::readMiscReg(int misc_reg, ThreadContext *tc)
583 return pmu->readMiscReg(misc_reg);
738 return getGenericTimer(tc).readMiscReg(misc_reg);
743 return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
1112 scr = readMiscReg(MISCREG_SCR, tc);
1122 scr = readMiscReg(MISCREG_SCR, tc);
1132 scr = readMiscReg(MISCREG_SCR, tc);
1142 scr = readMiscReg(MISCREG_SCR, tc);
1156 scr = readMiscReg(MISCREG_SCR, tc);
1171 scr = readMiscReg(MISCREG_SC
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H A Dinterrupts.hh138 HCR hcr = tc->readMiscReg(MISCREG_HCR);
143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
229 HCR hcr = tc->readMiscReg(MISCREG_HCR);
230 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dfaults.cc308 base = tc->readMiscReg(MISCREG_MVBAR);
311 base = tc->readMiscReg(MISCREG_HVBAR);
314 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
319 tc->readMiscReg(MISCREG_VBAR) : 0;
334 vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
338 vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
341 vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
426 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
452 AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1);
455 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL
[all...]
/gem5/src/arch/x86/
H A Dpseudo_inst.cc55 RegVal rflags = tc->readMiscReg(MISCREG_RFLAGS);
70 if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) {
85 tc->readMiscReg(MISCREG_CR2),
H A Disa.hh68 RegVal readMiscReg(int miscReg, ThreadContext *tc);
H A Dmmapped_ipr.hh66 RegVal data = htog(xc->readMiscReg(index));
/gem5/src/gpu-compute/
H A Dgpu_exec_context.cc57 GPUExecContext::readMiscReg(int opIdx) const function in class:GPUExecContext
60 return gpuISA->readMiscReg(opIdx);
H A Dgpu_exec_context.hh53 RegVal readMiscReg(int opIdx) const;
/gem5/src/arch/alpha/
H A Dlocked_mem.hh75 if (!xc->readMiscReg(MISCREG_LOCKFLAG))
78 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
110 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
111 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
H A Disa.hh78 RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
/gem5/src/arch/mips/
H A Dlocked_mem.hh65 if (!xc->readMiscReg(MISCREG_LLFLAG))
68 Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask;
103 bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG);
104 Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
H A Dutility.hh77 RegVal Stat = tc->readMiscReg(MISCREG_STATUS);
78 RegVal Dbg = tc->readMiscReg(MISCREG_DEBUG);
H A Dfaults.hh92 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
94 return tc->readMiscReg(MISCREG_EBASE);
170 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
241 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI);
247 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT);
283 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
H A Dfaults.cc106 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
109 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL);
127 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
/gem5/src/arch/hsail/
H A Dgpu_isa.hh62 readMiscReg(int opIdx) const function in class:HsailISA::GPUISA
/gem5/src/arch/riscv/
H A Dfaults.cc59 PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV);
61 STATUS status = tc->readMiscReg(MISCREG_STATUS);
66 bits(tc->readMiscReg(MISCREG_MIDELEG), _code) != 0) {
70 bits(tc->readMiscReg(MISCREG_SIDELEG), _code) != 0) {
75 bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) {
79 bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) {
130 Addr addr = tc->readMiscReg(tvec) >> 2;
131 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
144 STATUS status = tc->readMiscReg(MISCREG_STATUS);
H A Disa.hh78 RegVal readMiscReg(int misc_reg, ThreadContext *tc);
/gem5/src/arch/sparc/
H A Dremote_gdb.cc183 PSTATE pstate = context->readMiscReg(MISCREG_PSTATE);
185 r.fsr = htobe((uint32_t)context->readMiscReg(MISCREG_FSR));
198 r.fsr = htobe(context->readMiscReg(MISCREG_FSR));
199 r.fprs = htobe(context->readMiscReg(MISCREG_FPRS));
201 PSTATE pstate = context->readMiscReg(MISCREG_PSTATE);
203 context->readMiscReg(MISCREG_CWP) |
205 context->readMiscReg(MISCREG_ASI) << 24 |
245 PSTATE pstate = context()->readMiscReg(MISCREG_PSTATE);
/gem5/src/arch/power/
H A Disa.hh72 readMiscReg(int misc_reg, ThreadContext *tc) function in class:PowerISA::ISA
/gem5/src/arch/arm/insts/
H A Dmisc64.cc125 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
146 const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2);
147 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
148 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
149 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
295 const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3);
377 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);

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