/gem5/src/arch/arm/ |
H A D | isa_device.hh | 83 virtual RegVal readMiscReg(int misc_reg) = 0; 104 RegVal readMiscReg(int misc_reg) override;
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H A D | isa_device.cc | 69 DummyISADevice::readMiscReg(int misc_reg) function in class:ArmISA::DummyISADevice
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H A D | locked_mem.hh | 72 xc->readMiscReg(MISCREG_LOCKFLAG)); 73 if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 76 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 107 xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR)); 123 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 124 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask;
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H A D | utility.cc | 198 SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) : 199 tc->readMiscReg(MISCREG_SCR); 201 scr, tc->readMiscReg(MISCREG_CPSR)); 207 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); 214 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 221 TTBCR ttbcr = tc->readMiscReg(MISCREG_TTBCR); 242 return tc->readMiscReg(MISCREG_VMPIDR_EL2); 304 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); 329 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); 332 HCR hcr = tc->readMiscReg(MISCREG_HCR_EL [all...] |
H A D | interrupts.cc | 57 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 60 hcr = tc->readMiscReg(MISCREG_HCR); 65 scr = tc->readMiscReg(MISCREG_SCR); 67 scr = tc->readMiscReg(MISCREG_SCR_EL3);
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H A D | isa.cc | 452 ISA::readMiscReg(int misc_reg, ThreadContext *tc) 583 return pmu->readMiscReg(misc_reg); 738 return getGenericTimer(tc).readMiscReg(misc_reg); 743 return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 1112 scr = readMiscReg(MISCREG_SCR, tc); 1122 scr = readMiscReg(MISCREG_SCR, tc); 1132 scr = readMiscReg(MISCREG_SCR, tc); 1142 scr = readMiscReg(MISCREG_SCR, tc); 1156 scr = readMiscReg(MISCREG_SCR, tc); 1171 scr = readMiscReg(MISCREG_SC [all...] |
H A D | interrupts.hh | 138 HCR hcr = tc->readMiscReg(MISCREG_HCR); 143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 229 HCR hcr = tc->readMiscReg(MISCREG_HCR); 230 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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H A D | faults.cc | 308 base = tc->readMiscReg(MISCREG_MVBAR); 311 base = tc->readMiscReg(MISCREG_HVBAR); 314 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 319 tc->readMiscReg(MISCREG_VBAR) : 0; 334 vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 338 vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 341 vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 426 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 452 AA64MMFR1 mmfr1 = tc->readMiscReg(MISCREG_ID_AA64MMFR1_EL1); 455 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL [all...] |
/gem5/src/arch/x86/ |
H A D | pseudo_inst.cc | 55 RegVal rflags = tc->readMiscReg(MISCREG_RFLAGS); 70 if (!p->fixupStackFault(tc->readMiscReg(MISCREG_CR2))) { 85 tc->readMiscReg(MISCREG_CR2),
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H A D | isa.hh | 68 RegVal readMiscReg(int miscReg, ThreadContext *tc);
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H A D | mmapped_ipr.hh | 66 RegVal data = htog(xc->readMiscReg(index));
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/gem5/src/gpu-compute/ |
H A D | gpu_exec_context.cc | 57 GPUExecContext::readMiscReg(int opIdx) const function in class:GPUExecContext 60 return gpuISA->readMiscReg(opIdx);
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H A D | gpu_exec_context.hh | 53 RegVal readMiscReg(int opIdx) const;
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/gem5/src/arch/alpha/ |
H A D | locked_mem.hh | 75 if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 78 Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 110 bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 111 Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR);
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H A D | isa.hh | 78 RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
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/gem5/src/arch/mips/ |
H A D | locked_mem.hh | 65 if (!xc->readMiscReg(MISCREG_LLFLAG)) 68 Addr locked_addr = xc->readMiscReg(MISCREG_LLADDR) & cacheBlockMask; 103 bool lock_flag = xc->readMiscReg(MISCREG_LLFLAG); 104 Addr lock_addr = xc->readMiscReg(MISCREG_LLADDR);
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H A D | utility.hh | 77 RegVal Stat = tc->readMiscReg(MISCREG_STATUS); 78 RegVal Dbg = tc->readMiscReg(MISCREG_DEBUG);
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H A D | faults.hh | 92 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 94 return tc->readMiscReg(MISCREG_EBASE); 170 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); 241 EntryHiReg entryHi = tc->readMiscReg(MISCREG_ENTRYHI); 247 ContextReg context = tc->readMiscReg(MISCREG_CONTEXT); 283 StatusReg status = tc->readMiscReg(MISCREG_STATUS);
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H A D | faults.cc | 106 StatusReg status = tc->readMiscReg(MISCREG_STATUS); 109 SRSCtlReg srsCtl = tc->readMiscReg(MISCREG_SRSCTL); 127 CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
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/gem5/src/arch/hsail/ |
H A D | gpu_isa.hh | 62 readMiscReg(int opIdx) const function in class:HsailISA::GPUISA
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/gem5/src/arch/riscv/ |
H A D | faults.cc | 59 PrivilegeMode pp = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV); 61 STATUS status = tc->readMiscReg(MISCREG_STATUS); 66 bits(tc->readMiscReg(MISCREG_MIDELEG), _code) != 0) { 70 bits(tc->readMiscReg(MISCREG_SIDELEG), _code) != 0) { 75 bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) { 79 bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) { 130 Addr addr = tc->readMiscReg(tvec) >> 2; 131 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1) 144 STATUS status = tc->readMiscReg(MISCREG_STATUS);
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H A D | isa.hh | 78 RegVal readMiscReg(int misc_reg, ThreadContext *tc);
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/gem5/src/arch/sparc/ |
H A D | remote_gdb.cc | 183 PSTATE pstate = context->readMiscReg(MISCREG_PSTATE); 185 r.fsr = htobe((uint32_t)context->readMiscReg(MISCREG_FSR)); 198 r.fsr = htobe(context->readMiscReg(MISCREG_FSR)); 199 r.fprs = htobe(context->readMiscReg(MISCREG_FPRS)); 201 PSTATE pstate = context->readMiscReg(MISCREG_PSTATE); 203 context->readMiscReg(MISCREG_CWP) | 205 context->readMiscReg(MISCREG_ASI) << 24 | 245 PSTATE pstate = context()->readMiscReg(MISCREG_PSTATE);
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/gem5/src/arch/power/ |
H A D | isa.hh | 72 readMiscReg(int misc_reg, ThreadContext *tc) function in class:PowerISA::ISA
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/gem5/src/arch/arm/insts/ |
H A D | misc64.cc | 125 const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); 146 const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2); 147 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); 148 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); 149 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 295 const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3); 377 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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