| /gem5/util/m5/ |
| H A D | m5op_x86.S | 41 mov m5_mem@gotpcrel(%rip), %r11; \
42 mov (%r11), %r11; \
45 mov 0(%r11, %rax, 1), %rax; \
55 mov m5_mem, %r11; \
58 mov 0(%r11, %rax, 1), %rax; \
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| /gem5/ext/systemc/src/sysc/qt/md/ |
| H A D | powerpc_mach.s | 43 * r11-r12 volatile
255 mfcr r11 /* CR in r11 */
257 stw r11,CR_SAVE+BLOCKI_FSIZE(r1) /* save CR in the stack */
270 lwz r11,CR_SAVE+BLOCKI_FSIZE(r1) /* recover CR */
272 mtcr r11 /* restore CR */
316 lwz r11,CR_SAVE+BLOCKI_FSIZE(r1) /* recover CR */
318 mtcr r11 /* restore CR */
586 lwz r11,0(r1) /* get the backchain */
589 stw r3,P_T_SAVE(r11) /* sav
[all...] |
| H A D | powerpc_sys5.s | 36 * r11-r12 volatile
253 mfcr %r11 /* CR in r11 */
255 stw %r11,BLOCKI_CR_SAVE(%r1) /* save CR in the stack */
268 lwz %r11,BLOCKI_CR_SAVE(%r1) /* recover CR */
270 mtcr %r11 /* restore CR */
314 lwz %r11,BLOCKI_CR_SAVE(%r1) /* recover CR */
316 mtcr %r11 /* restore CR */
584 lwz %r11,0(%r1) /* get the backchain */
587 stw %r3,P_T_SAVE(%r11) /* sav
[all...] |
| H A D | hppa.s | 58 stw %r11,-96(%sp)
83 ldw -96(%sp),%r11
|
| /gem5/src/arch/x86/ |
| H A D | nativetrace.cc | 58 r11 = X86ISA::gtoh(r11);
85 r11 = tc->readIntReg(X86ISA::INTREG_R11);
152 oldR11Val = mState.r11;
153 oldRealR11Val = nState.r11;
167 checkR11Reg("r11", mState.r11, nState.r11);
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| H A D | nativetrace.hh | 61 uint64_t r11; member in struct:Trace::X86NativeTrace::ThreadState
|
| H A D | remote_gdb.hh | 111 uint64_t r11; member in struct:X86ISA::RemoteGDB::AMD64GdbRegCache::M5_ATTR_PACKED
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| H A D | remote_gdb.cc | 122 r.r11 = context->readIntReg(INTREG_R11);
174 context->setIntReg(INTREG_R11, r.r11);
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| /gem5/system/alpha/palcode/ |
| H A D | osfpal.S | 110 // r11 PS
201 sll r11, 63-osfps_v_mode, r25 // Shift mode up to MS bit
204 bis r11, r31, r12 // Save PS
228 stq r11, osfsf_ps(sp) // save old ps
229 bis r12, r31, r11 // update ps
271 and r11, osfps_m_mode, r10 // get mode bit
281 stq r11, osfsf_ps(sp) // save ps
298 bis r12, r31, r11 // set new ps
301 and r11, osfps_m_ipl, r14 // Isolate just new ipl (not really needed, since all non-ipl bits zeroed already)
492 sll r11, 6
[all...] |
| H A D | platform.S | 945 mtpr r11, ev5__dtb_cm // Restore Mbox current mode for ps
1002 mtpr r11, dtb_cm // Restore Mbox current mode
1419 lda r11, 0x7(r31) // Set shadow copy of PS - kern mode, IPL=7
2032 sll r11, 63-3, r25 // get mode to msb
2046 stq r11, osfsf_ps(sp) // save ps
2060 or r31, 7, r11 // get new ps (km, high ipl)
2162 and r11, osfps_m_mode, r1 // get mode bit
2164 bis r11, r31, r25 // save ps
2189 stq r11, osfsf_ps(sp) // save ps
2193 bis r25, r31, r11 // se
[all...] |
| /gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/int_datatype/ |
| H A D | int_datatype.cpp | 75 unsigned int r10, r11, r12, r13, r14, r15, r16, r17, r18, r19; local
99 r11 = op1 > op2; // Greater than
176 << "\n" << op1 << "\t > \t\t " << op2 << "\t = " << r11
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| /gem5/system/alpha/h/ |
| H A D | dc21164FromGasSources.h | 700 #define r11 $11 macro
804 #define p3 r11
805 // #define ps r11 /* Processor Status */
821 ** Processor Status ps, dtbCm, ipl, r11
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| /gem5/util/statetrace/arch/amd64/ |
| H A D | tracechild.cc | 102 case R11: return myregs.r11;
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| /gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_datatype/ |
| H A D | std_ulogic_datatype.cpp | 199 std_ulogic r10, r11, r12, r13, r14, r15, r16, r17, r18, r19; local
223 // r11 = op1 > op2; // Greater than
300 // << "\n" << op1 << "\t > \t\t " << op2 << "\t = " << r11
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| /gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_vector_datatype/ |
| H A D | std_ulogic_vector_datatype.cpp | 495 std_ulogic_vector<4> r9, r10, r11, r12, r13, r14; local
523 // r11 = op1 > op2; // Greater than
615 // << "\n" << op1 << "\t > \t\t " << op2 << "\t = " << r11
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| /gem5/src/cpu/kvm/ |
| H A D | x86_cpu.cc | 117 APPLY_IREG(r11, INTREG_R11); \
|