| /gem5/src/cpu/o3/ |
| H A D | FuncUnitConfig.py | 48 opList = [ OpDesc(opClass='IntAlu') ] variable in class:IntALU
52 opList = [ OpDesc(opClass='IntMult', opLat=3), variable in class:IntMultDiv
60 opList[1].opLat=1
65 opList = [ OpDesc(opClass='FloatAdd', opLat=2), variable in class:FP_ALU
71 opList = [ OpDesc(opClass='FloatMult', opLat=4), variable in class:FP_MultDiv
79 opList = [ OpDesc(opClass='SimdAdd'), variable in class:SIMD_Unit
108 opList = [ OpDesc(opClass='SimdPredAlu') ] variable in class:PredALU
112 opList = [ OpDesc(opClass='MemRead'), variable in class:ReadPort
117 opList = [ OpDesc(opClass='MemWrite'), variable in class:WritePort
122 opList variable in class:RdWrPort
127 opList = [ OpDesc(opClass='IprAccess', opLat = 3, pipelined = False) ] variable in class:IprPort
[all...] |
| /gem5/src/cpu/ |
| H A D | FuncUnit.py | 74 opList = VectorParam.OpDesc("operation classes for this FU type") variable in class:FUDesc
|
| H A D | func_unit.hh | 70 : SimObject(p), opDescList(p->opList), number(p->count) {};
|
| /gem5/configs/common/cores/arm/ |
| H A D | ex5_LITTLE.py | 43 opList = [ OpDesc(opClass='IntAlu', opLat=4) ] variable in class:ex5_LITTLE_Simple_Int
47 opList = [ OpDesc(opClass='IntMult', opLat=7) ] variable in class:ex5_LITTLE_Complex_IntMul
50 opList = [ OpDesc(opClass='IntDiv', opLat=9) ] variable in class:ex5_LITTLE_Complex_IntDiv
54 opList = [ OpDesc(opClass='SimdAdd', opLat=6), variable in class:ex5_LITTLE_FP
83 opList = [ OpDesc(opClass='MemRead',opLat=1), variable in class:ex5_LITTLE_MemFU
88 opList = [ OpDesc(opClass='IprAccess',opLat=1), variable in class:ex5_LITTLE_MiscFU
|
| H A D | O3_ARM_v7a.py | 36 opList = [ OpDesc(opClass='IntAlu', opLat=1) ] variable in class:O3_ARM_v7a_Simple_Int
41 opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True), variable in class:O3_ARM_v7a_Complex_Int
49 opList = [ OpDesc(opClass='SimdAdd', opLat=4), variable in class:O3_ARM_v7a_FP
82 opList = [ OpDesc(opClass='MemRead',opLat=2), variable in class:O3_ARM_v7a_Load
87 opList = [ OpDesc(opClass='MemWrite',opLat=2), variable in class:O3_ARM_v7a_Store
|
| H A D | ex5_big.py | 43 opList = [ OpDesc(opClass='IntAlu', opLat=1) ] variable in class:ex5_big_Simple_Int
48 opList = [ OpDesc(opClass='IntMult', opLat=4, pipelined=True), variable in class:ex5_big_Complex_Int
55 opList = [ OpDesc(opClass='SimdAdd', opLat=3), variable in class:ex5_big_FP
86 opList = [ OpDesc(opClass='MemRead',opLat=2) ] variable in class:ex5_big_Load
90 opList = [OpDesc(opClass='MemWrite',opLat=2) ] variable in class:ex5_big_Store
|
| /gem5/src/arch/hsail/ |
| H A D | operand.cc | 70 const BrigOperandCodeList *opList = local
74 obj->getBrigBaseData(opList->elements);
84 (unsigned*)obj->getData(opList->elements + 4 * (i + 1));
|