Searched refs:mach_inst (Results 1 - 12 of 12) sorted by relevance

/gem5/src/arch/generic/
H A Ddecode_cache.cc43 TheISA::ExtMachInst mach_inst, Addr addr)
46 if (si && (si->machInst == mach_inst))
49 auto iter = instMap.find(mach_inst);
55 si = decoder->decodeInst(mach_inst);
56 instMap[mach_inst] = si;
42 decode(TheISA::Decoder *decoder, TheISA::ExtMachInst mach_inst, Addr addr) argument
H A Ddecode_cache.hh55 /// @param mach_inst The binary instruction to decode.
58 TheISA::ExtMachInst mach_inst, Addr addr);
/gem5/src/arch/riscv/
H A Ddecoder.cc82 Decoder::decode(ExtMachInst mach_inst, Addr addr) argument
85 mach_inst, addr);
86 if (instMap.find(mach_inst) != instMap.end())
87 return instMap[mach_inst];
89 StaticInstPtr si = decodeInst(mach_inst);
90 instMap[mach_inst] = si;
H A Ddecoder.hh77 StaticInstPtr decodeInst(ExtMachInst mach_inst);
80 /// @param mach_inst The binary instruction to decode.
82 StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
/gem5/src/arch/alpha/
H A Ddecoder.hh94 StaticInstPtr decodeInst(ExtMachInst mach_inst);
97 /// @param mach_inst The binary instruction to decode.
100 decode(ExtMachInst mach_inst, Addr addr) argument
102 return defaultCache.decode(this, mach_inst, addr);
/gem5/src/arch/power/
H A Ddecoder.hh101 StaticInstPtr decodeInst(ExtMachInst mach_inst);
104 /// @param mach_inst The binary instruction to decode.
107 decode(ExtMachInst mach_inst, Addr addr) argument
109 return defaultCache.decode(this, mach_inst, addr);
/gem5/src/arch/mips/
H A Ddecoder.hh94 StaticInstPtr decodeInst(ExtMachInst mach_inst);
97 /// @param mach_inst The binary instruction to decode.
100 decode(ExtMachInst mach_inst, Addr addr) argument
102 return defaultCache.decode(this, mach_inst, addr);
/gem5/src/arch/arm/
H A Ddecoder.hh170 * @param mach_inst A pre-decoded instruction
173 StaticInstPtr decode(ExtMachInst mach_inst, Addr addr) argument
175 return defaultCache.decode(this, mach_inst, addr);
187 * @param mach_inst The binary instruction to decode.
190 StaticInstPtr decodeInst(ExtMachInst mach_inst);
/gem5/src/arch/sparc/
H A Ddecoder.hh108 StaticInstPtr decodeInst(ExtMachInst mach_inst);
111 /// @param mach_inst The binary instruction to decode.
114 decode(ExtMachInst mach_inst, Addr addr) argument
116 return defaultCache.decode(this, mach_inst, addr);
/gem5/src/cpu/minor/
H A Dfunc_unit.cc206 /* This should work for any ISA with a POD mach_inst */
207 TheISA::ExtMachInst mach_inst = inst->machInst; local
210 uint64_t mach_inst = 0;
221 (mach_inst & timing.mask) == timing.match)
226 i, timing.description, inst->disassemble(0), mach_inst,
236 " mach_inst: %16x\n",
237 inst->disassemble(0), mach_inst);
/gem5/src/arch/x86/
H A Ddecoder.hh343 StaticInstPtr decodeInst(ExtMachInst mach_inst);
346 /// @param mach_inst The binary instruction to decode.
348 StaticInstPtr decode(ExtMachInst mach_inst, Addr addr);
H A Ddecoder.cc682 Decoder::decode(ExtMachInst mach_inst, Addr addr) argument
684 auto iter = instMap->find(mach_inst);
688 StaticInstPtr si = decodeInst(mach_inst);
689 (*instMap)[mach_inst] = si;

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