Searched refs:l2 (Results 1 - 21 of 21) sorted by relevance

/gem5/configs/example/arm/
H A Dfs_power.py74 # Example to report l2 Cache overall_accesses
114 for l2 in root.system.bigCluster.l2.descendants():
115 if not isinstance(l2, m5.objects.Cache):
118 l2.default_p_state = "ON"
119 l2.power_model = L2PowerModel()
H A Ddevices.py156 self.l2 = self._l2_type()
159 self.toL2Bus.master = self.l2.cpu_side
164 self.l2.mem_side = bus.slave
/gem5/src/systemc/tests/systemc/communication/sc_signal_resolved/test01/
H A Dtest01.cpp51 sc_logic l2; local
74 l2 = sc_dt::sc_logic_value_t( j );
75 out2.write( l2 );
87 cout << l1 << " " << l2 << " -> " << in.read() << endl;
/gem5/src/systemc/tests/systemc/communication/sc_signal_resolved/test02/
H A Dtest02.cpp51 sc_logic l2; local
74 l2 = sc_dt::sc_logic_value_t( j );
75 out2.write( l2 );
87 cout << l1 << " " << l2 << " -> " << in.read() << endl;
/gem5/src/systemc/tests/systemc/communication/sc_signal_resolved/test03/
H A Dtest03.cpp52 sc_logic l2; local
75 l2 = sc_dt::sc_logic_value_t( j );
76 out2.write( l2 );
88 cout << l1 << " " << l2 << " -> " << in.read() << endl;
/gem5/src/systemc/tests/systemc/communication/sc_signal_rv/test01/
H A Dtest01.cpp51 sc_logic l2; local
74 l2 = sc_dt::sc_logic_value_t( j );
75 out2.write( sc_lv<1>( l2 ) );
87 cout << l1 << " " << l2 << " -> " << in.read() << endl;
/gem5/src/systemc/tests/systemc/communication/sc_signal_rv/test02/
H A Dtest02.cpp51 sc_logic l2; local
74 l2 = sc_dt::sc_logic_value_t( j );
75 out2.write( sc_lv<1>( l2 ) );
87 cout << l1 << " " << l2 << " -> " << in.read() << endl;
/gem5/src/systemc/tests/systemc/communication/sc_signal_rv/test03/
H A Dtest03.cpp52 sc_logic l2; local
75 l2 = sc_dt::sc_logic_value_t( j );
76 out2.write( sc_lv<1>( l2 ) );
88 cout << l1 << " " << l2 << " -> " << in.read() << endl;
/gem5/configs/common/
H A DCacheConfig.py101 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
106 system.l2.cpu_side = system.tol2bus.master
107 system.l2.mem_side = system.membus.slave
110 if system.l2.prefetcher != "Null":
111 print("Warning: l2-hwp-type is set (", hwpClass, "), but",
112 "the current l2 has a default Hardware Prefetcher",
113 "of type", type(system.l2.prefetcher), ", using the",
115 system.l2.prefetcher = hwpClass()
/gem5/util/
H A Drundiff284 my $l2 = $lines2[0];
286 if (!defined($l1) && !defined($l2)) {
291 if ($l1 eq $l2) {
H A Don-chip-network-power-area.py165 [l1,l2,l3] = lines[0].partition(" ")
/gem5/src/mem/ruby/network/simple/
H A DPerfectSwitch.hh57 bool operator<(const LinkOrder& l1, const LinkOrder& l2);
H A DPerfectSwitch.cc47 operator<(const LinkOrder& l1, const LinkOrder& l2) argument
49 return (l1.m_value < l2.m_value);
/gem5/ext/systemc/src/sysc/qt/md/
H A Dsparc.s86 ldd [%sp+ 8+96], %l2
/gem5/configs/splash2/
H A Drun.py204 system.l2 = L2(size = options.l2size, assoc = 8)
211 system.l2.cpu_side = system.toL2bus.master
212 system.l2.mem_side = system.membus.slave
H A Dcluster.py219 system.l2 = L2(size = options.l2size, assoc = 8)
226 system.l2.cpu_side = system.toL2bus.slave
227 system.l2.mem_side = system.membus.master
/gem5/src/arch/x86/
H A Disa.cc355 dr7.l2 = newDR7.l2;
357 if (dr7.l2 || dr7.g2) {
/gem5/util/stats/
H A Dstats.py372 misses = system.l2.overall_mshr_misses
/gem5/src/arch/x86/regs/
H A Dmisc.hh662 Bitfield<4> l2; member in namespace:X86ISA
/gem5/ext/googletest/googletest/test/
H A Dgtest-printers_test.cc954 const list<int> l2(a2, a2 + 3);
958 v.push_back(l2);
/gem5/util/streamline/
H A Dm5stats2streamline.py842 for l2 in range(num_l2):
844 name = re.sub("#", str(l2), item)

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