Searched refs:int_master (Results 1 - 14 of 14) sorted by relevance

/gem5/src/dev/x86/
H A DI82094AA.py39 int_master = MasterPort("Port for sending interrupt messages") variable in class:I82094AA
H A DSouthBridge.py113 self.io_apic.int_master = bus.slave
/gem5/src/arch/x86/
H A DX86LocalApic.py52 int_master = MasterPort("Port for sending interrupt messages") variable in class:X86LocalApic
/gem5/configs/learning_gem5/part1/
H A Dsimple.py78 system.cpu.interrupts[0].int_master = system.membus.slave
H A Dtwo_level.py130 system.cpu.interrupts[0].int_master = system.membus.slave
/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py77 system.cpu.interrupts[0].int_master = system.membus.slave
H A Dsimple_memobj.py75 system.cpu.interrupts[0].int_master = system.membus.slave
/gem5/tests/configs/
H A Dpc-simple-timing-ruby.py89 cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
/gem5/tests/gem5/cpu_tests/
H A Drun.py155 system.cpu.interrupts[0].int_master = system.membus.slave
/gem5/configs/learning_gem5/part3/
H A Dmsi_caches.py115 cpu.interrupts[0].int_master = self.sequencers[i].slave
H A Druby_caches_MI_example.py113 cpu.interrupts[0].int_master = self.sequencers[i].slave
/gem5/configs/example/
H A Dse.py268 system.cpu[i].interrupts[0].int_master = ruby_port.slave
H A Dapu_se.py465 system.cpu[i].interrupts[0].int_master = system.piobus.slave
507 system.cpu[cp_idx].interrupts[0].int_master = system.piobus.slave
H A Dfs.py180 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave

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