Searched refs:dc (Results 1 - 8 of 8) sorted by relevance

/gem5/src/cpu/testers/traffic_gen/
H A DBaseTrafficGen.py124 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
125 self.dcache = dc
126 self.port = dc.cpu_side
/gem5/src/cpu/
H A DBaseCPU.py245 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
247 self.dcache = dc
249 self.dcache_port = dc.cpu_side
268 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
270 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
/gem5/ext/ply/example/BASIC/
H A Dbasinterp.py34 self.dc = 0 # Initialize the data counter
243 if self.dc < len(self.data):
244 value = ('NUM',self.data[self.dc])
246 self.dc += 1
/gem5/ext/mcpat/
H A DxmlParser.cc2498 XMLNodeData *dc = childNode.d; local
2499 if ((!dc) || (!d)) return childNode;
2500 if (!dc->lpszName) {
2503 while (dc->nChild) {
2504 addChild(dc->pChild[0], j);
2509 if (dc->pParent) {
2510 if ((detachFromParent(dc) <= pos) && (dc->pParent == d)) pos--;
2511 } else dc->ref_count++;
2512 dc
[all...]
/gem5/src/arch/mips/
H A Dpra_constants.hh180 Bitfield<27> dc; member in namespace:MipsISA
/gem5/src/arch/riscv/
H A Dpra_constants.hh180 Bitfield<27> dc; member in namespace:RiscvISA
/gem5/src/arch/arm/
H A Dmiscregs_types.hh260 Bitfield<12> dc; member in namespace:ArmISA
H A Dtlb.cc790 // * It is a data cache invalidate (dc ivac) which requires write
1110 if (isStage2 || hcr.dc == 0 || isSecure ||

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