Searched refs:dc (Results 1 - 8 of 8) sorted by relevance
/gem5/src/cpu/testers/traffic_gen/ |
H A D | BaseTrafficGen.py | 124 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 125 self.dcache = dc 126 self.port = dc.cpu_side
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/gem5/src/cpu/ |
H A D | BaseCPU.py | 245 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None): 247 self.dcache = dc 249 self.dcache_port = dc.cpu_side 268 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, 270 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
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/gem5/ext/ply/example/BASIC/ |
H A D | basinterp.py | 34 self.dc = 0 # Initialize the data counter 243 if self.dc < len(self.data): 244 value = ('NUM',self.data[self.dc]) 246 self.dc += 1
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/gem5/ext/mcpat/ |
H A D | xmlParser.cc | 2498 XMLNodeData *dc = childNode.d; local 2499 if ((!dc) || (!d)) return childNode; 2500 if (!dc->lpszName) { 2503 while (dc->nChild) { 2504 addChild(dc->pChild[0], j); 2509 if (dc->pParent) { 2510 if ((detachFromParent(dc) <= pos) && (dc->pParent == d)) pos--; 2511 } else dc->ref_count++; 2512 dc [all...] |
/gem5/src/arch/mips/ |
H A D | pra_constants.hh | 180 Bitfield<27> dc; member in namespace:MipsISA
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/gem5/src/arch/riscv/ |
H A D | pra_constants.hh | 180 Bitfield<27> dc; member in namespace:RiscvISA
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/gem5/src/arch/arm/ |
H A D | miscregs_types.hh | 260 Bitfield<12> dc; member in namespace:ArmISA
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H A D | tlb.cc | 790 // * It is a data cache invalidate (dc ivac) which requires write 1110 if (isStage2 || hcr.dc == 0 || isSecure ||
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