Searched refs:bits (Results 1 - 25 of 120) sorted by relevance

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/gem5/src/arch/riscv/insts/
H A Dbitfields.hh6 #define CSRIMM bits(machInst, 19, 15)
7 #define FUNCT12 bits(machInst, 31, 20)
8 #define IMM5 bits(machInst, 11, 7)
9 #define IMM7 bits(machInst, 31, 25)
10 #define IMMSIGN bits(machInst, 31)
11 #define OPCODE bits(machInst, 6, 0)
/gem5/src/mem/ruby/common/
H A DSet.hh30 // >32 set lengths, using an array of ints w/ 32 bits/int
45 // Number of bits in use in this set.
48 std::bitset<NUMBER_BITS_PER_SET> bits; member in class:Set
56 fatal("Number of bits(%d) < size specified(%d). "
57 "Increase the number of bits and recompile.\n",
61 Set(const Set& obj) : m_nSize(obj.m_nSize), bits(obj.bits) {}
67 bits = obj.bits;
74 bits
217 out << "[Set (" << m_nSize << "): " << bits << "]"; local
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/gem5/ext/fputils/include/fputils/
H A Dfptypes.h50 uint64_t bits; member in union:__anon1
81 char bits[16]; member in union:__anon2
/gem5/src/arch/power/insts/
H A Dfloating.hh61 return ((bits(val_bits, 30, 23) == 0xFF) && bits(val_bits, 22, 0));
67 return ((bits(val_bits, 62, 52) == 0x7FF) && bits(val_bits, 51, 0));
90 return ((bits(val_bits, 30, 22) == 0x1FE) && bits(val_bits, 22, 0));
97 return (bits(val_bits, 30, 22) == 0x1FF);
104 return ((bits(val_bits, 30, 23) == 0xFF) && !bits(val_bits, 22, 0));
111 return ((bits(val_bit
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H A Dstatic_inst.hh54 uint32_t bits = value << ((7 - bf) * 4); local
56 return (cr & mask) | bits;
/gem5/src/base/filters/
H A Dbulk_bloom_filter.cc47 "Sectors need more bits than available");
60 int c = bits(addr, (offsetBits + (hash_number + 1) * sectorBits) - 1,
74 // permutes the original address bits according to Table 5
75 Addr part1 = bits(addr, offsetBits + 6, offsetBits),
76 part2 = bits(addr, offsetBits + 9),
77 part3 = bits(addr, offsetBits + 11),
78 part4 = bits(addr, offsetBits + 17),
79 part5 = bits(addr, offsetBits + 8, offsetBits + 7),
80 part6 = bits(addr, offsetBits + 10),
81 part7 = bits(add
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/gem5/src/base/
H A Dsat_counter.test.cc42 const unsigned bits = 3; local
43 const unsigned max_value = (1 << bits) - 1;
44 SatCounter counter(bits);
58 const unsigned bits = 3; local
59 SatCounter counter(bits);
73 const unsigned bits = 3; local
75 SatCounter counter(bits, initial_value);
87 const unsigned bits = 3; local
88 const unsigned max_value = (1 << bits) - 1;
89 SatCounter counter(bits);
104 const unsigned bits = 3; local
121 const unsigned bits = 3; local
145 const unsigned bits = 3; local
164 counter <<= bits; local
168 counter >>= bits; local
194 const unsigned bits = 3; local
223 const unsigned bits = 3; local
277 const unsigned bits = 3; local
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H A Dbitfield.hh72 bits(T val, int first, int last) function
84 bits(T val, int bit) function
86 return bits(val, bit, bit);
90 * Mask off the given bits in place like bits() but without shifting.
108 * Sign-extend an N-bit value to 64 bits.
115 int sign_bit = bits(val, N-1, N-1);
120 * Return val with bits first to last set to bit_val
144 * A convenience function to replace bits first to last of val with bit_val
201 if (bits(va
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/gem5/src/dev/x86/
H A Di8259.cc103 if (bits(val, 4)) {
106 edgeTriggered = bits(val, 3);
109 cascadeMode = !bits(val, 1);
112 expectICW4 = bits(val, 0);
118 } else if (bits(val, 4, 3) == 0) {
120 switch (bits(val, 7, 5)) {
138 int line = bits(val, 2, 0);
153 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
158 bits(va
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/gem5/src/dev/arm/
H A Dsmmu_v3_ptops.cc70 return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0;
95 case 1: return bits(va, 26+n, 30) << 3; break;
96 case 2: return bits(va, 29, 21) << 3; break;
97 case 3: return bits(va, 20, 12) << 3; break;
108 case 3: return bits(pte, 52) ? ~mask(16) : ~mask(12);
163 return stage2 ? bits(pte, 7, 6)==3 : bits(pte, 7)==0;
186 case 0: return bits(va, 47, 39) << 3; break;
187 case 1: return bits(v
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/gem5/src/arch/sparc/
H A Dvtophys.cc75 bool hpriv = bits(tlbdata,0,0);
76 // bool priv = bits(tlbdata,2,2);
77 bool addr_mask = bits(tlbdata,3,3);
78 bool data_real = !bits(tlbdata,5,5);
79 bool inst_real = !bits(tlbdata,4,4);
80 bool ctx_zero = bits(tlbdata,18,16) > 0;
81 int part_id = bits(tlbdata,15,8);
82 int pri_context = bits(tlbdata,47,32);
83 // int sec_context = bits(tlbdata,63,48);
112 va_tag = bits(add
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H A Dpagetable.hh67 bool valid() const { assert(populated); return !bits(entry,62,62); }
68 Addr va() const { assert(populated); return bits(entry,41,0); }
110 entry4u |= bits(entry,1,0) << 61; // size[1:0]
111 entry4u |= bits(entry,62,62) << 60; // nfo
112 entry4u |= bits(entry,12,12) << 59; // ie
113 entry4u |= bits(entry,2,2) << 48; // size[2]
115 entry4u |= bits(entry,61,61) << 6;; // locked
116 entry4u |= bits(entry,10,10) << 5; // cp
117 entry4u |= bits(entry,9,9) << 4; // cv
118 entry4u |= bits(entr
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/gem5/ext/dnet/
H A Daddr.h39 #define addr_pack(addr, type, bits, data, len) do { \
41 (addr)->addr_bits = bits; \
60 int addr_btos(uint16_t bits, struct sockaddr *sa);
61 int addr_stob(const struct sockaddr *sa, uint16_t *bits);
63 int addr_btom(uint16_t bits, void *mask, size_t size);
64 int addr_mtob(const void *mask, size_t size, uint16_t *bits);
/gem5/src/arch/sparc/insts/
H A Dbranch.hh77 template<int bits>
84 sext<bits + 2>((_machInst & mask(bits)) << 2))
97 sext<18>((bits(_machInst, 21, 20) << 16) |
98 (bits(_machInst, 13, 0) << 2)))
112 imm(sext<13>(bits(_machInst, 12, 0)))
H A Dinteger.hh90 IntOpImm(mnem, _machInst, __opClass, sext<10>(bits(_machInst, 9, 0)))
101 IntOpImm(mnem, _machInst, __opClass, sext<10>(bits(_machInst, 10, 0)))
112 IntOpImm(mnem, _machInst, __opClass, sext<13>(bits(_machInst, 12, 0)))
124 IntOpImm(mnem, _machInst, __opClass, bits(_machInst, 21, 0) << 10)
H A Dmem.hh67 Mem(mnem, _machInst, __opClass), imm(sext<13>(bits(_machInst, 12, 0)))
H A Dtrap.hh56 trapNum(bits(_machInst, 7, 0))
/gem5/src/arch/arm/
H A Dtable_walker.hh105 /** The raw bits of the entry */
141 return bits(data, 18);
144 /** Return the physcal address of the entry, bits in position*/
151 /** Return the physcal address of the entry, bits in position*/
160 /** Return the physical frame, bits shifted right */
165 return bits(data, 31, 20);
171 return !bits(data, 17);
177 return bits(data, 4);
183 return (bits(data, 15) << 2) | bits(dat
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/gem5/src/cpu/pred/
H A Dmultiperspective_perceptron_tage_8KB.cc145 size_t bits = 16; //global histories local
147 bits += (1 << logSizeUp) * pUpdateThresholdWidth;
149 bits += scCountersWidth * 2 * (1 << logBias); //2 bias arrays
151 bits += (gnb - 2) * (1 << logGnb) * (scCountersWidth - 1) +
154 bits += (pnb - 2) * (1 << logPnb) * (scCountersWidth - 1) +
157 bits += (lnb - 2) * (1 << logLnb) * (scCountersWidth - 1) +
160 bits += numEntriesFirstLocalHistories * lm[0];
162 bits += 16 * 16; // History stack
163 bits += 4; // History stack pointer
165 bits
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H A Dmultiperspective_perceptron_tage_64KB.cc163 size_t bits = 16; //global histories local
165 bits += (1 << logSizeUp) * pUpdateThresholdWidth;
167 bits += scCountersWidth * 2 * (1 << logBias); //2 bias arrays
169 bits += (gnb - 2) * (1 << logGnb) * (scCountersWidth - 1) +
172 bits += (pnb - 2) * (1 << logPnb) * (scCountersWidth - 1) +
175 bits += (lnb - 2) * (1 << logLnb) * (scCountersWidth - 1) +
178 bits += numEntriesFirstLocalHistories * lm[0];
180 bits += (snb - 2) * (1 << logSnb) * (scCountersWidth - 1) +
183 bits += numEntriesSecondLocalHistories * sm[0];
185 bits
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/gem5/util/
H A Dprotolib.py152 bits = value & 0x7f
155 out_file.write(struct.pack('<B', 0x80 | bits))
156 bits = value & 0x7f
158 out_file.write(struct.pack('<B', bits))
/gem5/src/arch/arm/insts/
H A Dpred_inst.hh127 if (bits(data, i)) {
142 bVal = bits(bigData, 6) ? (0x1F) : (0x20);
143 bigData = (bits(bigData, 5, 0) << 19) |
144 (bVal << 25) | (bits(bigData, 7) << 31);
148 bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
149 bigData = (bits(bigData, 5, 0) << 48) |
150 (bVal << 54) | (bits(bigData, 7) << 63);
172 repData = bits(data, 6) ? 0x3 : 0;
173 bigData = (bits(bigData, 5, 0) << 6) |
174 (repData << 12) | (bits(~bigDat
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/gem5/src/mem/cache/tags/indexing_policies/
H A Dskewed_associative.cc53 panic_if(setShift + 2 * (msbShift + 1) > 64, "Unsuported number of bits " \
64 // Get relevant bits
65 const uint8_t lsb = bits<Addr>(addr, 0);
66 const uint8_t msb = bits<Addr>(addr, msbShift);
76 // Get relevant bits. The original MSB is one bit away on the current MSB
79 const uint8_t msb = bits<Addr>(addr, msbShift - 1);
80 const uint8_t xor_bit = bits<Addr>(addr, msbShift);
91 // Assume an address of size A bits can be decomposed into
93 // addr0 (M bits) = Block offset;
94 // addr1 (N bits)
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/gem5/src/arch/mips/
H A Dutility.cc132 fcsr = bits(fcsr, 31, cc_idx + 1) << (cc_idx + 1) |
134 bits(fcsr, cc_idx - 1, 0);
161 return (bits(val_bits, 30, 23) == 0xFF);
167 return (bits(val_bits, 62, 52) == 0x7FF);
184 return (bits(val_bits, 30, 22) == 0x1FE);
190 return (bits(val_bits, 62, 51) == 0xFFE);
206 return (bits(val_bits, 30, 22) == 0x1FF);
212 return (bits(val_bits, 62, 51) == 0xFFF);
/gem5/src/mem/cache/prefetch/
H A Dirregular_stream_buffer.hh74 AddressMapping(unsigned bits) : address(0), counter(bits) argument

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