Searched refs:TheISA (Results 1 - 25 of 125) sorted by relevance

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/gem5/src/kern/
H A Dsystem_events.cc41 using namespace TheISA;
46 TheISA::PCState oldPC M5_VAR_USED = tc->pcState();
49 TheISA::skipFunction(tc);
/gem5/src/arch/generic/
H A Ddecode_cache.hh39 namespace TheISA namespace
50 DecodeCache::InstMap<TheISA::ExtMachInst> instMap;
57 StaticInstPtr decode(TheISA::Decoder * const decoder,
58 TheISA::ExtMachInst mach_inst, Addr addr);
H A Dtraits.hh59 mode(const TheISA::PCState&) argument
H A Ddecode_cache.cc42 BasicDecodeCache::decode(TheISA::Decoder *decoder,
43 TheISA::ExtMachInst mach_inst, Addr addr)
/gem5/src/cpu/pred/
H A Dras.hh57 TheISA::PCState top()
65 void push(const TheISA::PCState &return_addr);
75 void restore(unsigned top_entry_idx, const TheISA::PCState &restored);
90 std::vector<TheISA::PCState> addrStack;
H A Dbtb.hh52 TheISA::PCState target;
78 TheISA::PCState lookup(Addr instPC, ThreadID tid);
92 void update(Addr instPC, const TheISA::PCState &targetPC,
H A Dras.cc51 ReturnAddrStack::push(const TheISA::PCState &return_addr)
74 const TheISA::PCState &restored)
H A Dindirect.hh51 virtual bool lookup(Addr br_addr, TheISA::PCState& br_target,
59 const TheISA::PCState& target, ThreadID tid) = 0;
/gem5/src/cpu/
H A Dstatic_inst.cc40 static TheISA::ExtMachInst nopMachInst;
55 advancePC(TheISA::PCState &pcState) const override
83 StaticInst::hasBranchTarget(const TheISA::PCState &pc, ThreadContext *tc,
84 TheISA::PCState &tgt) const
106 TheISA::PCState
107 StaticInst::branchTarget(const TheISA::PCState &pc) const
114 TheISA::PCState
H A Ddecode_cache.hh41 namespace TheISA namespace
60 Value items[TheISA::PageBytes];
85 Addr page_addr = addr & ~(TheISA::PageBytes - 1);
108 page_addr = page_addr & ~(TheISA::PageBytes - 1);
125 return page->items[addr & (TheISA::PageBytes - 1)];
H A Dinteltrace.hh49 const StaticInstPtr _staticInst, TheISA::PCState _pc,
68 const StaticInstPtr staticInst, TheISA::PCState pc,
H A Dthread_context.cc64 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
73 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
82 for (int i = 0; i < TheISA::NumVecRegs; ++i) {
84 const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
85 const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
92 for (int i = 0; i < TheISA::NumVecPredRegs; ++i) {
94 const TheISA::VecPredRegContainer& t1 = one->readVecPredReg(rid);
95 const TheISA::VecPredRegContainer& t2 = two->readVecPredReg(rid);
101 for (int i = 0; i < TheISA::NumMiscRegs; ++i) {
110 for (int i = 0; i < TheISA
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H A Dsimple_thread.hh98 typedef TheISA::MachInst MachInst;
99 using VecRegContainer = TheISA::VecRegContainer;
100 using VecElem = TheISA::VecElem;
101 using VecPredRegContainer = TheISA::VecPredRegContainer;
106 RegVal floatRegs[TheISA::NumFloatRegs];
107 RegVal intRegs[TheISA::NumIntRegs];
108 VecRegContainer vecRegs[TheISA::NumVecRegs];
109 VecPredRegContainer vecPredRegs[TheISA::NumVecPredRegs];
111 RegVal ccRegs[TheISA::NumCCRegs];
113 TheISA
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H A Dexetrace.hh51 const StaticInstPtr _staticInst, TheISA::PCState _pc,
72 const StaticInstPtr staticInst, TheISA::PCState pc,
H A Dinteltrace.cc43 using namespace TheISA;
/gem5/src/mem/
H A Dfs_translating_port_proxy.cc79 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
83 paddr = TheISA::vtophys(_tc,gen.addr());
85 paddr = TheISA::vtophys(gen.addr());
98 for (ChunkGenerator gen(addr, size, TheISA::PageBytes); !gen.done();
102 paddr = TheISA::vtophys(_tc,gen.addr());
104 paddr = TheISA::vtophys(gen.addr());
116 for (ChunkGenerator gen(address, size, TheISA::PageBytes); !gen.done();
120 paddr = TheISA::vtophys(_tc,gen.addr());
122 paddr = TheISA::vtophys(gen.addr());
/gem5/src/cpu/minor/
H A Dscoreboard.hh96 numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
97 TheISA::NumFloatRegs +
98 (TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg) +
99 TheISA::NumVecPredRegs),
H A Dscoreboard.cc66 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
71 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
72 TheISA::NumFloatRegs + reg.index();
76 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
77 TheISA::NumFloatRegs + reg.flatIndex();
81 scoreboard_index = TheISA::NumIntRegs + TheISA
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/gem5/src/cpu/o3/
H A Drename_map.cc121 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
123 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
125 vecMap.init(TheISA::NumVecRegs, &(freeList->vecList), (RegIndex)-1);
127 vecElemMap.init(TheISA::NumVecRegs * NVecElems,
130 predMap.init(TheISA::NumVecPredRegs, &(freeList->predList), (RegIndex)-1);
132 ccMap.init(TheISA::NumCCRegs, &(freeList->ccList), (RegIndex)-1);
145 regFile->numVecPhysRegs() - TheISA::NumVecRegs,
162 TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg,
166 freeList->addRegs(range.first + TheISA
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H A Dimpl.hh56 typedef TheISA::MachInst MachInst;
/gem5/src/sim/
H A Dinsttracer.hh69 TheISA::PCState pc;
100 ::VecRegContainer<TheISA::VecRegSizeBytes>* as_vec;
101 ::VecPredRegContainer<TheISA::VecPredRegSizeBits,
102 TheISA::VecPredRegHasPackedRepr>* as_pred;
152 TheISA::PCState _pc,
201 setData(::VecRegContainer<TheISA::VecRegSizeBytes>& d)
203 data.as_vec = new ::VecRegContainer<TheISA::VecRegSizeBytes>(d);
208 setData(::VecPredRegContainer<TheISA::VecPredRegSizeBits,
209 TheISA::VecPredRegHasPackedRepr>& d)
212 TheISA
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H A Darguments.cc55 return TheISA::getArgument(tc, number, size, fp);
/gem5/src/kern/freebsd/
H A Devents.cc56 uint64_t time = TheISA::getArgument(tc, arg_num, (uint16_t)-1, false);
/gem5/src/kern/linux/
H A Dhelpers.cc70 de.ts_nsec = TheISA::gtoh(de.ts_nsec);
71 de.len = TheISA::gtoh(de.len);
72 de.text_len = TheISA::gtoh(de.text_len);
112 proxy.read<uint32_t>(addr_lb_len, TheISA::GuestByteOrder);
114 proxy.read<uint32_t>(addr_first, TheISA::GuestByteOrder);
116 proxy.read<uint32_t>(addr_next, TheISA::GuestByteOrder);
/gem5/src/dev/arm/
H A Drealview.cc59 using namespace TheISA;

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