/gem5/src/mem/slicc/symbols/ |
H A D | State.py | 30 class State(Symbol): class in inherits:Symbol 32 return "[State: %s]" % self.ident 36 class WildcardState(State): 38 return "[State: *]" 42 __all__ = [ "State" ]
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H A D | __init__.py | 32 from slicc.symbols.State import State
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H A D | Transition.py | 29 from slicc.symbols.State import WildcardState
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/gem5/src/arch/x86/ |
H A D | decoder.hh | 163 //State machine state 177 enum State { enum in class:X86ISA::Decoder 197 State state; 200 State doResetState(); 201 State doFromCacheState(); 202 State doPrefixState(uint8_t); 203 State doVex2Of2State(uint8_t); 204 State doVex2Of3State(uint8_t); 205 State doVex3Of3State(uint8_t); 206 State doVexOpcodeStat [all...] |
H A D | decoder.cc | 42 Decoder::State 143 Decoder::State 177 Decoder::State 181 State nextState = PrefixState; 244 Decoder::State 274 Decoder::State 315 Decoder::State 352 Decoder::State 376 Decoder::State 379 State nextStat [all...] |
H A D | pagetable_walker.hh | 79 // State to track each walk of the page table 84 enum State { enum in class:X86ISA::Walker::WalkerState 99 State state; 100 State nextState; 147 // State for timing and atomic accesses (need multiple per walker in 150 // State for functional accesses (only need one of these per walker)
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/gem5/src/mem/slicc/ast/ |
H A D | TypeFieldStateAST.py | 28 from slicc.symbols import Event, State 44 if not str(type) == "State": 45 self.error("State Declaration must be of type State.") 55 self.error("State declaration not part of a machine.") 56 s = State(self.symtab, self.field_id, self.location, self.pairs)
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H A D | TypeFieldEnumAST.py | 29 from slicc.symbols import Event, State, RequestType 42 if str(type) == "State": 43 self.error("States must in a State Declaration, not a normal enum.")
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/gem5/src/cpu/o3/ |
H A D | lsq.hh | 267 enum class State class 275 State _state; 277 void setState(const State& newState) { _state = newState; } 306 _state(State::NotIssued), _senderState(nullptr), 322 : _state(State::NotIssued), _senderState(nullptr), 589 return _state == State::Translation; 602 return _state == State::Translation && 616 return _state == State::PartialFault; 622 return (_state == State::Request || 694 using State [all...] |
H A D | lsq_impl.hh | 794 setState(State::Request); 796 setState(State::Fault); 839 setState(State::Request); 842 setState(State::PartialFault); 846 setState(State::Fault); 865 setState(State::Translation); 958 setState(State::Translation);
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/gem5/src/dev/arm/ |
H A D | vgic.hh | 126 Bitfield<29,28> State; member in class:VGic 154 /* State per CPU. EVERYTHING should be in this struct and simply replicated 226 if (vid->LR[i].State & LR_PENDING) 235 if (vid->LR[i].State) 247 if ((vid->LR[i].State & LR_PENDING) && (vid->LR[i].Priority < prio)) { 258 if (vid->LR[i].State &&
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H A D | gic_v3_cpu_interface.cc | 432 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 488 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID; 658 // Maintenance Interrupt State Register 694 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) && 1457 ich_lrc.State = requested_ich_lrc.State; 1502 ich_lr_el2.State = requested_ich_lr_el2.State; 1637 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) || 1638 (ich_lr_el2.State [all...] |
H A D | vgic.cc | 125 lr->State = LR_ACTIVE; 202 if (!vid->LR[i].State) 211 if (!vid->LR[i].State) 269 lr->State = 0; 271 // LRs have EOI=1 and State=INVALID! 414 if (!tvid->LR[i].State && tvid->LR[i].EOI) {
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H A D | gic_v3_cpu_interface.hh | 218 Bitfield<63, 62> State; member in class:Gicv3CPUInterface 235 Bitfield<31, 30> State; member in class:Gicv3CPUInterface
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/gem5/src/mem/ |
H A D | xbar.hh | 207 enum State { IDLE, BUSY, RETRY }; enum in class:BaseXBar::Layer 209 State state;
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/gem5/src/mem/cache/ |
H A D | cache_blk.hh | 105 typedef unsigned State; typedef in class:CacheBlk 108 State status; 186 const State needed_bits = BlkWritable | BlkValid; 198 const State needed_bits = BlkReadable | BlkValid;
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H A D | cache.cc | 601 CacheBlk::State old_state = blk ? blk->status : 0;
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H A D | base.cc | 1342 CacheBlk::State old_state = blk ? blk->status : 0;
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