Searched refs:State (Results 1 - 18 of 18) sorted by relevance

/gem5/src/mem/slicc/symbols/
H A DState.py30 class State(Symbol): class in inherits:Symbol
32 return "[State: %s]" % self.ident
36 class WildcardState(State):
38 return "[State: *]"
42 __all__ = [ "State" ]
H A D__init__.py32 from slicc.symbols.State import State
H A DTransition.py29 from slicc.symbols.State import WildcardState
/gem5/src/arch/x86/
H A Ddecoder.hh163 //State machine state
177 enum State { enum in class:X86ISA::Decoder
197 State state;
200 State doResetState();
201 State doFromCacheState();
202 State doPrefixState(uint8_t);
203 State doVex2Of2State(uint8_t);
204 State doVex2Of3State(uint8_t);
205 State doVex3Of3State(uint8_t);
206 State doVexOpcodeStat
[all...]
H A Ddecoder.cc42 Decoder::State
143 Decoder::State
177 Decoder::State
181 State nextState = PrefixState;
244 Decoder::State
274 Decoder::State
315 Decoder::State
352 Decoder::State
376 Decoder::State
379 State nextStat
[all...]
H A Dpagetable_walker.hh79 // State to track each walk of the page table
84 enum State { enum in class:X86ISA::Walker::WalkerState
99 State state;
100 State nextState;
147 // State for timing and atomic accesses (need multiple per walker in
150 // State for functional accesses (only need one of these per walker)
/gem5/src/mem/slicc/ast/
H A DTypeFieldStateAST.py28 from slicc.symbols import Event, State
44 if not str(type) == "State":
45 self.error("State Declaration must be of type State.")
55 self.error("State declaration not part of a machine.")
56 s = State(self.symtab, self.field_id, self.location, self.pairs)
H A DTypeFieldEnumAST.py29 from slicc.symbols import Event, State, RequestType
42 if str(type) == "State":
43 self.error("States must in a State Declaration, not a normal enum.")
/gem5/src/cpu/o3/
H A Dlsq.hh267 enum class State class
275 State _state;
277 void setState(const State& newState) { _state = newState; }
306 _state(State::NotIssued), _senderState(nullptr),
322 : _state(State::NotIssued), _senderState(nullptr),
589 return _state == State::Translation;
602 return _state == State::Translation &&
616 return _state == State::PartialFault;
622 return (_state == State::Request ||
694 using State
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H A Dlsq_impl.hh794 setState(State::Request);
796 setState(State::Fault);
839 setState(State::Request);
842 setState(State::PartialFault);
846 setState(State::Fault);
865 setState(State::Translation);
958 setState(State::Translation);
/gem5/src/dev/arm/
H A Dvgic.hh126 Bitfield<29,28> State; member in class:VGic
154 /* State per CPU. EVERYTHING should be in this struct and simply replicated
226 if (vid->LR[i].State & LR_PENDING)
235 if (vid->LR[i].State)
247 if ((vid->LR[i].State & LR_PENDING) && (vid->LR[i].Priority < prio)) {
258 if (vid->LR[i].State &&
H A Dgic_v3_cpu_interface.cc432 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
488 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
658 // Maintenance Interrupt State Register
694 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
1457 ich_lrc.State = requested_ich_lrc.State;
1502 ich_lr_el2.State = requested_ich_lr_el2.State;
1637 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1638 (ich_lr_el2.State
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H A Dvgic.cc125 lr->State = LR_ACTIVE;
202 if (!vid->LR[i].State)
211 if (!vid->LR[i].State)
269 lr->State = 0;
271 // LRs have EOI=1 and State=INVALID!
414 if (!tvid->LR[i].State && tvid->LR[i].EOI) {
H A Dgic_v3_cpu_interface.hh218 Bitfield<63, 62> State; member in class:Gicv3CPUInterface
235 Bitfield<31, 30> State; member in class:Gicv3CPUInterface
/gem5/src/mem/
H A Dxbar.hh207 enum State { IDLE, BUSY, RETRY }; enum in class:BaseXBar::Layer
209 State state;
/gem5/src/mem/cache/
H A Dcache_blk.hh105 typedef unsigned State; typedef in class:CacheBlk
108 State status;
186 const State needed_bits = BlkWritable | BlkValid;
198 const State needed_bits = BlkReadable | BlkValid;
H A Dcache.cc601 CacheBlk::State old_state = blk ? blk->status : 0;
H A Dbase.cc1342 CacheBlk::State old_state = blk ? blk->status : 0;

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