Lines Matching refs:State
432 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
488 ich_lr_el2.State = ICH_LR_EL2_STATE_INVALID;
658 // Maintenance Interrupt State Register
694 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
1457 ich_lrc.State = requested_ich_lrc.State;
1502 ich_lr_el2.State = requested_ich_lr_el2.State;
1637 if (((ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE) ||
1638 (ich_lr_el2.State == ICH_LR_EL2_STATE_ACTIVE_PENDING)) &&
1874 ich_lr_el.State = ICH_LR_EL2_STATE_ACTIVE;
1909 ich_lr_el2.State = ich_lr_el2.State & ~ICH_LR_EL2_STATE_ACTIVE;
2123 if (ich_lr_el2.State != Gicv3::INT_PENDING) {
2427 // - ICH_LR<n>_EL2.State is 0b00 (ICH_LR_EL2_STATE_INVALID).
2437 if ((ich_lr_el2.State == ICH_LR_EL2_STATE_INVALID) &&
2467 // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits
2476 if (ich_lr_el2.State != ICH_LR_EL2_STATE_INVALID) {
2480 if (ich_lr_el2.State == ICH_LR_EL2_STATE_PENDING) {