Searched refs:RubySequencer (Results 1 - 18 of 18) sorted by relevance

/gem5/configs/ruby/
H A DGarnet_standalone.py85 cpu_seq = RubySequencer(icache = cache,
H A DAMD_Base_Constructor.py82 self.sequencer = RubySequencer()
90 self.sequencer1 = RubySequencer()
H A DGPU_RfO.py117 self.sequencer = RubySequencer()
125 self.sequencer1 = RubySequencer()
174 self.sequencer = RubySequencer()
203 self.sequencer = RubySequencer()
236 self.sequencer = RubySequencer()
257 self.sequencer = RubySequencer()
H A DGPU_VIPER.py103 self.sequencer = RubySequencer()
111 self.sequencer1 = RubySequencer()
159 self.sequencer = RubySequencer()
190 self.sequencer = RubySequencer()
224 self.sequencer = RubySequencer()
H A DMOESI_AMD_Base.py104 self.sequencer = RubySequencer()
112 self.sequencer1 = RubySequencer()
H A DGPU_VIPER_Region.py104 self.sequencer = RubySequencer()
112 self.sequencer1 = RubySequencer()
160 self.sequencer = RubySequencer()
191 self.sequencer = RubySequencer()
H A DMI_example.py97 cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
H A DGPU_VIPER_Baseline.py103 self.sequencer = RubySequencer()
111 self.sequencer1 = RubySequencer()
159 self.sequencer = RubySequencer()
190 self.sequencer = RubySequencer()
H A DMESI_Two_Level.py107 cpu_seq = RubySequencer(version = i, icache = l1i_cache,
H A DMOESI_CMP_directory.py118 cpu_seq = RubySequencer(version=i, icache=l1i_cache,
H A DMOESI_hammer.py114 cpu_seq = RubySequencer(version=i, icache=l1i_cache,
H A DMOESI_CMP_token.py122 cpu_seq = RubySequencer(version=i, icache=l1i_cache,
H A DMESI_Three_Level.py117 cpu_seq = RubySequencer(version = i * num_cpus_per_cluster + j,
/gem5/src/mem/ruby/system/
H A DSequencer.py59 class RubySequencer(RubyPort): class in inherits:RubyPort
60 type = 'RubySequencer'
H A DSequencer.cc37 #include "debug/RubySequencer.hh"
477 DPRINTF(RubySequencer, "read data %s\n", data);
485 DPRINTF(RubySequencer, "swap data %s\n", data);
491 DPRINTF(RubySequencer, "set data %s\n", data);
499 DPRINTF(RubySequencer, "hitCallback %s 0x%x using RubyTester\n",
549 DPRINTF(RubySequencer, "Issuing SC\n");
552 DPRINTF(RubySequencer, "Issuing LL\n");
565 DPRINTF(RubySequencer, "Issuing Locked RMW Write\n");
568 DPRINTF(RubySequencer, "Issuing Locked RMW Read\n");
/gem5/configs/learning_gem5/part3/
H A Dtest_caches.py78 self.sequencers = [RubySequencer(version = i,
H A Dmsi_caches.py84 self.sequencers = [RubySequencer(version = i,
H A Druby_caches_MI_example.py84 self.sequencers = [RubySequencer(version = i,

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