Searched refs:Q_BASE_ADDR_MASK (Results 1 - 3 of 3) sorted by relevance

/gem5/src/dev/arm/
H A Dsmmu_v3_cmdexec.cc74 (smmu.regs.cmdq_base & Q_BASE_ADDR_MASK) +
H A Dsmmu_v3_defs.hh95 Q_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL, enumerator in enum:__anon14
H A Dsmmu_v3_transl.cc1307 (smmu.regs.eventq_base & Q_BASE_ADDR_MASK) +

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