/gem5/src/arch/sparc/ |
H A D | handlers.hh | 45 const MachInst fillHandler64[numFillInsts] = 47 htog<MachInst>(0x87802016), // wr %g0, ASI_AIUP, %asi 48 htog<MachInst>(0xe0dba7ff), // ldxa [%sp + BIAS + (0*8)] %asi, %l0 49 htog<MachInst>(0xe2dba807), // ldxa [%sp + BIAS + (1*8)] %asi, %l1 50 htog<MachInst>(0xe4dba80f), // ldxa [%sp + BIAS + (2*8)] %asi, %l2 51 htog<MachInst>(0xe6dba817), // ldxa [%sp + BIAS + (3*8)] %asi, %l3 52 htog<MachInst>(0xe8dba81f), // ldxa [%sp + BIAS + (4*8)] %asi, %l4 53 htog<MachInst>(0xeadba827), // ldxa [%sp + BIAS + (5*8)] %asi, %l5 54 htog<MachInst>(0xecdba82f), // ldxa [%sp + BIAS + (6*8)] %asi, %l6 55 htog<MachInst>( [all...] |
H A D | types.hh | 40 typedef uint32_t MachInst; typedef in namespace:SparcISA 43 typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
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H A D | decoder.hh | 66 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 75 asi << (sizeof(MachInst) * 8))); 78 << (sizeof(MachInst) * 8));
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/gem5/src/arch/null/ |
H A D | types.hh | 47 typedef uint32_t MachInst; typedef in namespace:NullISA 49 class PCState : public GenericISA::UPCState<MachInst> 53 typedef GenericISA::UPCState<MachInst> Base;
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/gem5/src/arch/riscv/ |
H A D | decoder.cc | 40 static const MachInst LowerBitMask = (1 << sizeof(MachInst) * 4) - 1; 41 static const MachInst UpperBitMask = LowerBitMask << sizeof(MachInst) * 4; 53 Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 58 bool aligned = pc.pc() % sizeof(MachInst) == 0; 68 emi |= (inst & LowerBitMask) << sizeof(MachInst)*4; 73 emi = (inst & UpperBitMask) >> sizeof(MachInst)*4; 103 nextPC.npc(nextPC.instAddr() + sizeof(MachInst) / 2); 105 nextPC.npc(nextPC.instAddr() + sizeof(MachInst)); [all...] |
H A D | types.hh | 54 typedef uint32_t MachInst; typedef in namespace:RiscvISA 57 class PCState : public GenericISA::UPCState<MachInst> 77 return npc() != pc() + sizeof(MachInst)/2 || 80 return npc() != pc() + sizeof(MachInst) ||
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/gem5/src/arch/generic/ |
H A D | types.hh | 140 template <class MachInst> 158 npc(val + sizeof(MachInst)); 173 return this->npc() != this->pc() + sizeof(MachInst); 181 _npc += sizeof(MachInst); 185 template <class MachInst> 187 operator<<(std::ostream & os, const SimplePCState<MachInst> &pc) 194 template <class MachInst> 195 class UPCState : public SimplePCState<MachInst> 198 typedef SimplePCState<MachInst> Base; 231 return this->npc() != this->pc() + sizeof(MachInst) || [all...] |
/gem5/src/arch/alpha/ |
H A D | types.hh | 40 typedef uint32_t MachInst; typedef in namespace:AlphaISA 43 typedef GenericISA::SimplePCState<MachInst> PCState;
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H A D | stacktrace.cc | 237 StackTrace::decodeStack(MachInst inst, int &disp) 245 const MachInst mem_mask = 0xffff0000; 246 const MachInst lda_pattern = 0x23de0000; 247 const MachInst lda_disp_mask = 0x0000ffff; 259 const MachInst intop_mask = 0xffe01fff; 260 const MachInst addq_pattern = 0x43c0141e; 261 const MachInst subq_pattern = 0x43c0153e; 262 const MachInst intop_disp_mask = 0x001fe000; 278 StackTrace::decodeSave(MachInst inst, int ®, int &disp) 286 const MachInst stq_mas [all...] |
/gem5/src/cpu/o3/ |
H A D | impl.hh | 55 /** The type of MachInst. */ 56 typedef TheISA::MachInst MachInst; typedef in struct:O3CPUImpl
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/gem5/src/arch/hsail/ |
H A D | gpu_types.hh | 56 // The MachInst is a representation of an instruction 62 struct MachInst struct in namespace:HsailISA
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H A D | gpu_decoder.hh | 56 GPUStaticInst* decode(MachInst machInst);
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/gem5/src/arch/mips/ |
H A D | stacktrace.cc | 128 StackTrace::decodeStack(MachInst inst, int &disp) 136 const MachInst mem_mask = 0xffff0000; 137 const MachInst lda_pattern = 0x23de0000; 138 const MachInst lda_disp_mask = 0x0000ffff; 150 const MachInst intop_mask = 0xffe01fff; 151 const MachInst addq_pattern = 0x43c0141e; 152 const MachInst subq_pattern = 0x43c0153e; 153 const MachInst intop_disp_mask = 0x001fe000; 169 StackTrace::decodeSave(MachInst inst, int ®, int &disp) 177 const MachInst stq_mas [all...] |
H A D | stacktrace.hh | 63 typedef MipsISA::MachInst MachInst; typedef in class:MipsISA::StackTrace 71 bool decodeSave(MachInst inst, int ®, int &disp); 72 bool decodeStack(MachInst inst, int &disp);
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/gem5/src/arch/power/insts/ |
H A D | mem.hh | 50 MemOp(const char *mnem, MachInst _machInst, OpClass __opClass) 71 MemDispOp(const char *mnem, MachInst _machInst, OpClass __opClass)
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H A D | misc.hh | 47 MiscOp(const char *mnem, MachInst _machInst, OpClass __opClass)
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H A D | condition.hh | 52 CondLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass) 75 CondMoveOp(const char *mnem, MachInst _machInst, OpClass __opClass)
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H A D | branch.hh | 79 BranchPCRel(const char *mnem, MachInst _machInst, OpClass __opClass) 109 BranchNonPCRel(const char *mnem, MachInst _machInst, OpClass __opClass) 140 BranchCond(const char *mnem, MachInst _machInst, OpClass __opClass) 188 BranchPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass) 218 BranchNonPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass) 245 BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass)
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H A D | integer.hh | 62 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass) 110 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) 132 IntShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass) 155 IntRotateOp(const char *mnem, MachInst _machInst, OpClass __opClass)
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/gem5/src/arch/arm/ |
H A D | stacktrace.hh | 66 typedef ArmISA::MachInst MachInst; typedef in class:ArmISA::StackTrace 74 bool decodeSave(MachInst inst, int ®, int &disp); 75 bool decodeStack(MachInst inst, int &disp);
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H A D | decoder.hh | 64 MachInst data; 133 * MachInst blocks (which correspond to the size of a typical 143 * sizeof(MachInst)). 149 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
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/gem5/src/arch/power/ |
H A D | decoder.hh | 68 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst) 77 moreBytes(MachInst machInst)
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H A D | types.hh | 41 typedef uint32_t MachInst; typedef in namespace:PowerISA 81 typedef GenericISA::SimplePCState<MachInst> PCState;
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/gem5/src/arch/riscv/insts/ |
H A D | standard.hh | 66 ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass) 96 CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
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H A D | unknown.hh | 55 Unknown(MachInst _machInst)
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