Searched refs:MachInst (Results 1 - 25 of 69) sorted by relevance

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/gem5/src/arch/sparc/
H A Dhandlers.hh45 const MachInst fillHandler64[numFillInsts] =
47 htog<MachInst>(0x87802016), // wr %g0, ASI_AIUP, %asi
48 htog<MachInst>(0xe0dba7ff), // ldxa [%sp + BIAS + (0*8)] %asi, %l0
49 htog<MachInst>(0xe2dba807), // ldxa [%sp + BIAS + (1*8)] %asi, %l1
50 htog<MachInst>(0xe4dba80f), // ldxa [%sp + BIAS + (2*8)] %asi, %l2
51 htog<MachInst>(0xe6dba817), // ldxa [%sp + BIAS + (3*8)] %asi, %l3
52 htog<MachInst>(0xe8dba81f), // ldxa [%sp + BIAS + (4*8)] %asi, %l4
53 htog<MachInst>(0xeadba827), // ldxa [%sp + BIAS + (5*8)] %asi, %l5
54 htog<MachInst>(0xecdba82f), // ldxa [%sp + BIAS + (6*8)] %asi, %l6
55 htog<MachInst>(
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H A Dtypes.hh40 typedef uint32_t MachInst; typedef in namespace:SparcISA
43 typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
H A Ddecoder.hh66 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
75 asi << (sizeof(MachInst) * 8)));
78 << (sizeof(MachInst) * 8));
/gem5/src/arch/null/
H A Dtypes.hh47 typedef uint32_t MachInst; typedef in namespace:NullISA
49 class PCState : public GenericISA::UPCState<MachInst>
53 typedef GenericISA::UPCState<MachInst> Base;
/gem5/src/arch/riscv/
H A Ddecoder.cc40 static const MachInst LowerBitMask = (1 << sizeof(MachInst) * 4) - 1;
41 static const MachInst UpperBitMask = LowerBitMask << sizeof(MachInst) * 4;
53 Decoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
58 bool aligned = pc.pc() % sizeof(MachInst) == 0;
68 emi |= (inst & LowerBitMask) << sizeof(MachInst)*4;
73 emi = (inst & UpperBitMask) >> sizeof(MachInst)*4;
103 nextPC.npc(nextPC.instAddr() + sizeof(MachInst) / 2);
105 nextPC.npc(nextPC.instAddr() + sizeof(MachInst));
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H A Dtypes.hh54 typedef uint32_t MachInst; typedef in namespace:RiscvISA
57 class PCState : public GenericISA::UPCState<MachInst>
77 return npc() != pc() + sizeof(MachInst)/2 ||
80 return npc() != pc() + sizeof(MachInst) ||
/gem5/src/arch/generic/
H A Dtypes.hh140 template <class MachInst>
158 npc(val + sizeof(MachInst));
173 return this->npc() != this->pc() + sizeof(MachInst);
181 _npc += sizeof(MachInst);
185 template <class MachInst>
187 operator<<(std::ostream & os, const SimplePCState<MachInst> &pc)
194 template <class MachInst>
195 class UPCState : public SimplePCState<MachInst>
198 typedef SimplePCState<MachInst> Base;
231 return this->npc() != this->pc() + sizeof(MachInst) ||
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/gem5/src/arch/alpha/
H A Dtypes.hh40 typedef uint32_t MachInst; typedef in namespace:AlphaISA
43 typedef GenericISA::SimplePCState<MachInst> PCState;
H A Dstacktrace.cc237 StackTrace::decodeStack(MachInst inst, int &disp)
245 const MachInst mem_mask = 0xffff0000;
246 const MachInst lda_pattern = 0x23de0000;
247 const MachInst lda_disp_mask = 0x0000ffff;
259 const MachInst intop_mask = 0xffe01fff;
260 const MachInst addq_pattern = 0x43c0141e;
261 const MachInst subq_pattern = 0x43c0153e;
262 const MachInst intop_disp_mask = 0x001fe000;
278 StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
286 const MachInst stq_mas
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/gem5/src/cpu/o3/
H A Dimpl.hh55 /** The type of MachInst. */
56 typedef TheISA::MachInst MachInst; typedef in struct:O3CPUImpl
/gem5/src/arch/hsail/
H A Dgpu_types.hh56 // The MachInst is a representation of an instruction
62 struct MachInst struct in namespace:HsailISA
H A Dgpu_decoder.hh56 GPUStaticInst* decode(MachInst machInst);
/gem5/src/arch/mips/
H A Dstacktrace.cc128 StackTrace::decodeStack(MachInst inst, int &disp)
136 const MachInst mem_mask = 0xffff0000;
137 const MachInst lda_pattern = 0x23de0000;
138 const MachInst lda_disp_mask = 0x0000ffff;
150 const MachInst intop_mask = 0xffe01fff;
151 const MachInst addq_pattern = 0x43c0141e;
152 const MachInst subq_pattern = 0x43c0153e;
153 const MachInst intop_disp_mask = 0x001fe000;
169 StackTrace::decodeSave(MachInst inst, int &reg, int &disp)
177 const MachInst stq_mas
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H A Dstacktrace.hh63 typedef MipsISA::MachInst MachInst; typedef in class:MipsISA::StackTrace
71 bool decodeSave(MachInst inst, int &reg, int &disp);
72 bool decodeStack(MachInst inst, int &disp);
/gem5/src/arch/power/insts/
H A Dmem.hh50 MemOp(const char *mnem, MachInst _machInst, OpClass __opClass)
71 MemDispOp(const char *mnem, MachInst _machInst, OpClass __opClass)
H A Dmisc.hh47 MiscOp(const char *mnem, MachInst _machInst, OpClass __opClass)
H A Dcondition.hh52 CondLogicOp(const char *mnem, MachInst _machInst, OpClass __opClass)
75 CondMoveOp(const char *mnem, MachInst _machInst, OpClass __opClass)
H A Dbranch.hh79 BranchPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
109 BranchNonPCRel(const char *mnem, MachInst _machInst, OpClass __opClass)
140 BranchCond(const char *mnem, MachInst _machInst, OpClass __opClass)
188 BranchPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
218 BranchNonPCRelCond(const char *mnem, MachInst _machInst, OpClass __opClass)
245 BranchRegCond(const char *mnem, MachInst _machInst, OpClass __opClass)
H A Dinteger.hh62 IntOp(const char *mnem, MachInst _machInst, OpClass __opClass)
110 IntImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
132 IntShiftOp(const char *mnem, MachInst _machInst, OpClass __opClass)
155 IntRotateOp(const char *mnem, MachInst _machInst, OpClass __opClass)
/gem5/src/arch/arm/
H A Dstacktrace.hh66 typedef ArmISA::MachInst MachInst; typedef in class:ArmISA::StackTrace
74 bool decodeSave(MachInst inst, int &reg, int &disp);
75 bool decodeStack(MachInst inst, int &disp);
H A Ddecoder.hh64 MachInst data;
133 * MachInst blocks (which correspond to the size of a typical
143 * sizeof(MachInst)).
149 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
/gem5/src/arch/power/
H A Ddecoder.hh68 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
77 moreBytes(MachInst machInst)
H A Dtypes.hh41 typedef uint32_t MachInst; typedef in namespace:PowerISA
81 typedef GenericISA::SimplePCState<MachInst> PCState;
/gem5/src/arch/riscv/insts/
H A Dstandard.hh66 ImmOp(const char *mnem, MachInst _machInst, OpClass __opClass)
96 CSROp(const char *mnem, MachInst _machInst, OpClass __opClass)
H A Dunknown.hh55 Unknown(MachInst _machInst)

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