Searched refs:MISCREG_ID_AA64ISAR0_EL1 (Results 1 - 6 of 6) sorted by relevance

/gem5/src/arch/arm/
H A Disa.cc351 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
395 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
396 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
399 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
400 miscRegs[MISCREG_ID_AA64ISAR0_EL1], 23, 20,
1098 case MISCREG_ID_AA64ISAR0_EL1:
H A Dprocess.cc222 const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
H A Dmiscregs.hh454 MISCREG_ID_AA64ISAR0_EL1, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc1744 return MISCREG_ID_AA64ISAR0_EL1;
3946 InitReg(MISCREG_ID_AA64ISAR0_EL1)
/gem5/src/arch/arm/insts/
H A Dmisc64.cc248 case MISCREG_ID_AA64ISAR0_EL1:
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc414 { "id_aa64isar0_el1", MISCREG_ID_AA64ISAR0_EL1 },

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