Searched refs:ExternalSlave (Results 1 - 16 of 16) sorted by relevance

/gem5/src/mem/
H A Dexternal_slave.hh43 * ExternalSlave is a memory object representing a binding from
56 * exception of getAddrRanges which is provided by the ExternalSlave
64 #include "params/ExternalSlave.hh"
67 class ExternalSlave : public SimObject class in inherits:SimObject
74 ExternalSlave &owner;
78 ExternalSlave &owner_) :
100 const std::string &name, ExternalSlave &owner,
128 ExternalSlave(ExternalSlaveParams *params);
H A Dexternal_slave.cc52 class StubSlavePort : public ExternalSlave::ExternalPort
68 ExternalSlave &owner_) :
69 ExternalSlave::ExternalPort(name_, owner_),
83 ExternalSlave::Handler
86 ExternalSlave::ExternalPort *getExternalPort(
88 ExternalSlave &owner,
174 std::map<std::string, ExternalSlave::Handler *>
175 ExternalSlave::portHandlers;
178 ExternalSlave::ExternalPort::getAddrRanges() const
183 ExternalSlave function in class:ExternalSlave
[all...]
H A DExternalSlave.py41 class ExternalSlave(SimObject): class in inherits:SimObject
42 type = 'ExternalSlave'
/gem5/util/tlm/src/
H A Dsc_slave_port.hh71 class SCSlavePort : public ExternalSlave::Port
116 ExternalSlave &owner_);
123 class SCSlavePortHandler : public ExternalSlave::Handler
131 ExternalSlave::Port *getExternalPort(const std::string &name,
132 ExternalSlave &owner,
H A Dsc_slave_port.cc367 ExternalSlave &owner_) :
368 ExternalSlave::Port(name_, owner_),
387 ExternalSlave::Port*
389 ExternalSlave &owner,
H A Dsim_control.cc82 ExternalSlave::registerHandler("tlm_slave", new SCSlavePortHandler(*this));
/gem5/ext/sst/
H A Dgem5.hh63 public ExternalSlave::Handler,
90 virtual ExternalSlave::Port *getExternalPort(
91 const std::string &name, ExternalSlave &owner,
H A DExtSlave.hh63 class ExtSlave : public ExternalSlave::Port {
101 ExtSlave(gem5Component*, Output&, ExternalSlave&, std::string&);
H A Dgem5.cc115 ExternalSlave ::registerHandler("sst", this);
261 ExternalSlave::Port*
263 ExternalSlave &owner, const std::string &port_data)
H A DExtSlave.cc56 ::ExternalSlave& port, std::string &name) :
/gem5/util/tlm/conf/
H A Dtlm_slave.py64 system.tlm = ExternalSlave()
H A Dtlm_elastic_slave.py107 system.tlm = ExternalSlave()
/gem5/configs/common/
H A DMemConfig.py180 system.external_memory = m5.objects.ExternalSlave(
189 subsystem.external_memory = m5.objects.ExternalSlave(
H A DCacheConfig.py207 # ExternalSlave provides a "port", but when that port connects to a cache,
211 class ExternalCache(ExternalSlave):
215 return super(ExternalSlave, cls).__getattr__(attr)
220 return super(ExternalSlave, cls).__setattr__(attr, value)
H A DFSConfig.py355 self.iocache = ExternalSlave(port_data="iocache",
/gem5/util/tlm/examples/
H A Dtlm_elastic_slave_with_l2.py115 system.tlm = ExternalSlave()

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