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36// Copyright 2009-2014 Sandia Coporation.  Under the terms
37// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
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40// Copyright (c) 2009-2014, Sandia Corporation
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42//
43// For license information, see the LICENSE file in the current directory.
44
45#ifndef EXT_SST_GEM5_HH
46#define EXT_SST_GEM5_HH
47
48#include <string>
49#include <vector>
50
51#include <core/sst_config.h>
52#include <core/component.h>
53
54#include <sim/simulate.hh>
55
56#include "ExtMaster.hh"
57#include "ExtSlave.hh"
58
59namespace SST {
60namespace gem5 {
61
62class gem5Component : public SST::Component,
63                      public ExternalSlave::Handler,
64                      public ExternalMaster::Handler {
65private:
66
67    Output dbg;
68    Output info;
69    uint64_t sim_cycles;
70    uint64_t clocks_processed;
71
72    std::vector<ExtMaster*> masters;
73    std::vector<ExtSlave*> slaves;
74
75    void splitCommandArgs(std::string &cmd, std::vector<char*> &args);
76    void initPython(int argc, char *argv[]);
77
78public:
79    gem5Component(ComponentId_t id, Params &params);
80    ~gem5Component();
81    virtual void init(unsigned);
82    virtual void setup();
83    virtual void finish();
84    bool clockTick(Cycle_t);
85
86    virtual ExternalMaster::Port *getExternalPort(
87        const std::string &name, ExternalMaster &owner,
88        const std::string &port_data);
89
90    virtual ExternalSlave::Port *getExternalPort(
91        const std::string &name, ExternalSlave &owner,
92        const std::string &port_data);
93};
94
95}
96}
97
98#endif
99