Searched refs:write (Results 651 - 675 of 747) sorted by relevance

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/gem5/src/python/m5/util/
H A Ddot_writer.py354 callgraph.write(dot_filename)
374 dvfsgraph.write(dot_filename)
/gem5/src/base/
H A Dcp_annotate.cc144 osbin->write((char*)&ah, sizeof(AnnotateHeader));
926 osbin->write((char*)&annotateIdx[x], sizeof(uint64_t));
930 osbin->write((char*)&ah, sizeof(AnnotateHeader));
963 osbin->write((char*)&(an->time), sizeof(an->time));
964 osbin->write((char*)&(an->orig_data), sizeof(an->orig_data));
965 osbin->write((char*)&(an->sm), sizeof(an->sm));
966 osbin->write((char*)&(an->stq), sizeof(an->stq));
967 osbin->write((char*)&(an->op), sizeof(an->op));
968 osbin->write((char*)&(an->flag), sizeof(an->flag));
969 osbin->write((cha
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H A Dremote_gdb.cc310 case GdbWriteWp: return "write watchpoint";
526 if (::write(fd, &b, sizeof(b)) == sizeof(b))
529 throw BadClient("Couldn't write data to the debugger.");
646 BaseRemoteGDB::write(Addr vaddr, size_t size, const char *data) function in class:BaseRemoteGDB
652 DPRINTF(GDBWrite, "write: writing memory location zero!\n");
657 DPRINTFN("write: addr=%#x, size=%d", vaddr, size);
792 // write general registers
804 // write memory
808 // write register
824 // write memor
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/gem5/src/cpu/o3/
H A Dlsq.hh868 * Attempts to write back stores until all cache ports are used or the
985 /** Returns whether or not there are any stores to write back to memory. */
988 /** Returns whether or not a specific thread has any stores to write back
993 /** Returns the number of stores a specific thread has to write back. */
996 /** Returns if the LSQ will write back to memory this cycle. */
998 /** Returns if the LSQ of a specific thread will write back to memory this
1016 Fault write(LSQRequest* req, uint8_t *data, int store_idx);
1130 LSQ<Impl>::write(LSQRequest* req, uint8_t *data, int store_idx) function in class:LSQ::LSQ
1134 return thread.at(tid).write(req, data, store_idx);
H A Dcpu.hh350 /** Sets a misc. register, including any side effects the write
731 /** CPU write function, forwards write to LSQ. */
732 Fault write(LSQRequest* req, uint8_t *data, int store_idx) function in class:FullO3CPU
734 return this->iew.ldstQueue.write(req, data, store_idx);
/gem5/ext/testlib/
H A Dhelper.py55 :params stdout: Iterable of items to write to as we read from the
58 :params stderr: Iterable of items to write to as we read from the
72 if hasattr(stdout_redirect, 'write'):
74 if hasattr(stderr_redirect, 'write'):
85 r.write(line)
402 tempfile_.write(line)
H A Dhandlers.py142 ).stderr.write(record['buffer'])
147 ).stdout.write(record['buffer'])
/gem5/src/arch/arm/kvm/
H A Dgic.cc228 MuxingKvmGic::write(PacketPtr pkt) function in class:MuxingKvmGic
231 return GicV2::write(pkt);
/gem5/src/dev/arm/
H A Dhdlcd.cc256 // write registers and frame buffer
258 HDLcd::write(PacketPtr pkt) function in class:HDLcd
268 DPRINTF(HDLcd, "write register 0x%04x: 0x%x\n", daddr, data);
431 panic("Tried to write HDLCD register that doesn't exist\n", offset);
585 imgWriter->write(*pic->stream());
H A Dpl111.hh268 /** Helper to write out bitmaps */
373 Tick write(PacketPtr pkt) override;
H A Dhdlcd.hh108 Tick write(PacketPtr pkt) override;
352 /** Helper to write out bitmaps */
/gem5/util/
H A Dqdo234 log.write(shell.full_output)
/gem5/src/dev/
H A Ddma_device.cc182 // Increment the data pointer on a write
416 buffer.write(tmp_buffer.begin(), xfer_size);
468 buffer.write(event->data(), event->requestSize());
H A Dintel_8254_timer.cc170 Intel8254Timer::Counter::write(const uint8_t data) function in class:Intel8254Timer::Counter
205 panic("Only LSB/MSB read/write is implemented.\n");
/gem5/src/arch/sparc/
H A Dprocess.cc359 // write contents to stack
375 initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
381 initVirtMem.write(auxv_array_end, zero);
/gem5/src/dev/net/
H A Dsinicreg.hh177 bool write; member in struct:Sinic::Regs::Info
/gem5/util/statetrace/arch/arm/
H A Dtracechild.cc89 sent = write(socket, messagePtr, toSend);
/gem5/ext/systemc/src/sysc/communication/
H A Dsc_clock.cpp270 sc_clock::write( const bool& /* value */ ) function in class:sc_core::sc_clock
/gem5/util/m5/
H A Dm5.c123 ret = write(dest_fid, base, len);
125 perror("Failed to write file");
128 fprintf(stderr, "Failed to write file: "
129 "Unhandled short write\n");
/gem5/src/arch/mips/
H A Dtlb.cc162 warn("Attempted to write at index (%d) beyond TLB size (%d)",
250 .desc("DTB write hits")
255 .desc("DTB write misses")
261 .desc("DTB write accesses")
300 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
/gem5/src/arch/power/
H A Dtlb.cc164 warn("Attempted to write at index (%d) beyond TLB size (%d)",
247 .desc("DTB write hits")
252 .desc("DTB write misses")
258 .desc("DTB write accesses")
301 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
/gem5/src/cpu/kvm/
H A Dbase.cc1115 BaseKvmCPU::doMMIOAccess(Addr paddr, void *data, int size, bool write) argument
1128 BaseTLB::Mode tlb_mode(write ? BaseTLB::Write : BaseTLB::Read);
1134 const MemCmd cmd(write ? MemCmd::WriteReq : MemCmd::ReadReq);
1142 const Cycles ipr_delay(write ?
/gem5/src/dev/alpha/
H A Dtsunami_io.cc154 TsunamiIO::write(PacketPtr pkt) function in class:TsunamiIO
159 DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n",
H A Dbackdoor.cc201 AlphaBackdoor::write(PacketPtr pkt) function in class:AlphaBackdoor
/gem5/src/dev/serial/
H A Duart8250.cc178 Uart8250::write(PacketPtr pkt) function in class:Uart8250
186 DPRINTF(Uart, " write register %#x value %#x\n", daddr,
191 if (!(LCR & 0x80)) { // write byte

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