| /gem5/configs/dram/ |
| H A D | low_power_sweep.py | 92 system = System(membus = IOXBar(width = 32))
|
| H A D | lat_mem_rd.py | 104 system = System(membus = SystemXBar(width = 32))
|
| /gem5/src/base/loader/ |
| H A D | coff_sym.h | 285 unsigned fBitfield : 1; /* set if bit width is specified */
346 width in bits if (bit field), width in bits.
358 coff_int width; /* width for non-default sized struc fields */ member in union:__anon21
|
| /gem5/src/sim/ |
| H A D | process.hh | 77 virtual RegVal getSyscallArg(ThreadContext *tc, int &i, int width);
|
| H A D | process.cc | 405 Process::getSyscallArg(ThreadContext *tc, int &i, int width) argument
|
| /gem5/util/tlm/src/ |
| H A D | sc_master_port.cc | 151 unsigned width = trans.get_streaming_width(); local
158 if (width < len) { // is this a burst request?
|
| /gem5/configs/example/arm/ |
| H A D | devices.py | 155 self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
282 self.toL3Bus = L2XBar(width=64)
|
| /gem5/ext/drampower/src/ |
| H A D | MemoryPowerModel.cc | 140 // memArchSpec.width represents the number of data (dq) pins.
142 int64_t dqPlusDqsBits = memArchSpec.width + memArchSpec.width / 8;
144 int64_t dqPlusDqsPlusMaskBits = memArchSpec.width + memArchSpec.width / 8 + memArchSpec.width / 8;
|
| /gem5/src/arch/arm/ |
| H A D | isa.hh | 383 if (cpsr.width == 0) {
425 assert(cpsr.width);
430 assert(!cpsr.width);
|
| H A D | types.hh | 666 Bitfield<4> width; member in namespace:ArmISA
672 return ((OperatingMode64)(uint8_t)mode).width == 0;
|
| H A D | faults.cc | 612 pc.aarch64(!cpsr.width);
613 pc.nextAArch64(!cpsr.width);
682 mode.width = 0;
702 pc.aarch64(!cpsr.width);
703 pc.nextAArch64(!cpsr.width);
|
| /gem5/src/cpu/simple/ |
| H A D | atomic.cc | 83 width(p->width), locked(false),
655 for (int i = 0; i < width || locked; ++i) {
|
| /gem5/src/arch/arm/kvm/ |
| H A D | armv8_cpu.cc | 225 if (cpsr.width) {
293 if (cpsr.width) {
|
| /gem5/src/systemc/tlm_bridge/ |
| H A D | tlm_to_gem5.cc | 246 unsigned width = trans.get_streaming_width(); local
253 if (width < len) { // is this a burst request?
|
| /gem5/src/arch/hsail/ |
| H A D | Brig_new.hpp | 1350 BrigWidth8_t width; member in struct:BrigInstBr
1382 BrigWidth8_t width; member in struct:BrigInstLane
1391 BrigWidth8_t width; member in struct:BrigInstMem
1514 BrigUInt64 width; //.acc=subItem<UInt64> //.wtype=UInt64 member in struct:BrigOperandConstantImage
|
| /gem5/src/dev/arm/ |
| H A D | pl111.hh | 274 /** Frame buffer width - pixels per line */
275 uint16_t width; member in class:Pl111
|
| H A D | hdlcd.cc | 684 inform("PixelPump width: %u", t.width);
|
| /gem5/src/mem/ |
| H A D | drampower.cc | 63 archSpec.width = p->device_bus_width;
|
| /gem5/src/arch/x86/ |
| H A D | process.cc | 1100 I386Process::getSyscallArg(ThreadContext *tc, int &i, int width) argument
1102 assert(width == 32 || width == 64);
1105 if (width == 64)
|
| /gem5/src/cpu/pred/ |
| H A D | multiperspective_perceptron_tage.cc | 456 short int max_weight = (1 << (specs[i]->width - 1)) - 1;
457 short int min_weight = -(1 << (specs[i]->width - 1));
|
| /gem5/ext/mcpat/cacti/ |
| H A D | cacti_interface.h | 478 double width; member in class:mem_array
|
| /gem5/tests/configs/ |
| H A D | gpu-ruby.py | 110 parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \
111 help="VGPR to Coalescer (Global Memory) data bus width in bytes")
112 parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \
113 help="Coalescer to VGPR (Global Memory) data bus width in bytes")
281 system.piobus = IOXBar(width=32, response_latency=0,
|
| /gem5/src/arch/hsail/insts/ |
| H A D | decl.hh | 966 uint8_t width; member in class:HsailISA::Barrier
973 width = (uint8_t)((Brig::BrigInstBr*)ib)->width;
|
| H A D | mem.hh | 212 Brig::BrigWidth8_t width; member in class:HsailISA::LdInstBase
238 width = ldst->width;
254 width = BRIG_WIDTH_1;
|
| /gem5/ext/pybind11/tools/ |
| H A D | mkdoc.py | 165 wrapper.width = 70
|