/gem5/src/cpu/pred/ |
H A D | 2bit_local.cc | 66 LocalBP::btbUpdate(ThreadID tid, Addr branch_addr, void * &bp_history) argument 74 LocalBP::lookup(ThreadID tid, Addr branch_addr, void * &bp_history) argument 93 LocalBP::update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history, argument 135 LocalBP::uncondBranch(ThreadID tid, Addr pc, void *&bp_history) argument
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H A D | tage_sc_l.cc | 129 ThreadID tid, Addr pc, TAGEBase::BranchInfo* bi) 134 tableIndices[i] = gindex(tid, pc, i); 135 tableTags[i] = gtag(tid, pc, i); 144 Addr t = (pc ^ (threadHistory[tid].pathHist & 157 t = (pc ^ (threadHistory[tid].pathHist & ((1 << histLengths[1]) - 1))) 180 TAGE_SC_L_TAGE::gindex(ThreadID tid, Addr pc, int bank) const argument 190 threadHistory[tid].computeIndices[bank].comp ^ 191 F(threadHistory[tid].pathHist, hlen, bank); 266 ThreadID tid, Addr branch_pc, bool taken, TAGEBase::BranchInfo* b, 275 ThreadHistory& tHist = threadHistory[tid]; 128 calculateIndicesAndTags( ThreadID tid, Addr pc, TAGEBase::BranchInfo* bi) argument 265 updateHistories( ThreadID tid, Addr branch_pc, bool taken, TAGEBase::BranchInfo* b, bool speculative, const StaticInstPtr &inst, Addr target) argument 289 squash(ThreadID tid, bool taken, TAGEBase::BranchInfo *bi, Addr target) argument 365 predict(ThreadID tid, Addr branch_pc, bool cond_branch, void* &b) argument 413 update(ThreadID tid, Addr branch_pc, bool taken, void *bp_history, bool squashed, const StaticInstPtr & inst, Addr corrTarget) argument [all...] |
H A D | multiperspective_perceptron_tage_8KB.hh | 62 int gPredictions(ThreadID tid, Addr branch_pc, 67 void gUpdates(ThreadID tid, Addr pc, bool taken,
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H A D | tage_sc_l_8KB.hh | 59 uint16_t gtag(ThreadID tid, Addr pc, int bank) const override; 96 int gPredictions( ThreadID tid, Addr branch_pc, 105 void gUpdates(ThreadID tid, Addr pc, bool taken, BranchInfo* bi,
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H A D | multiperspective_perceptron_tage.hh | 77 void updateHistories(ThreadID tid, Addr branch_pc, bool taken, 162 bool scPredict(ThreadID tid, Addr branch_pc, bool cond_branch, 168 void condBranchUpdate(ThreadID tid, Addr branch_pc, bool taken, 214 unsigned int getIndex(ThreadID tid, MPPTAGEBranchInfo &bi, 216 int computePartialSum(ThreadID tid, MPPTAGEBranchInfo &bi) const; 217 void updatePartial(ThreadID tid, MPPTAGEBranchInfo &bi, bool taken); 218 void updateHistories(ThreadID tid, MPPTAGEBranchInfo &bi, bool taken); 226 bool lookup(ThreadID tid, Addr instPC, void * &bp_history) override; 228 void update(ThreadID tid, Addr instPC, bool taken, 232 void uncondBranch(ThreadID tid, Add [all...] |
H A D | tage_base.hh | 194 * @param tid The thread ID used to select the 199 virtual int gindex(ThreadID tid, Addr pc, int bank) const; 212 * @param tid the thread ID used to select the 217 virtual uint16_t gtag(ThreadID tid, Addr pc, int bank) const; 269 * @param tid The thread ID to select the global 276 void update(ThreadID tid, Addr branch_pc, bool taken, BranchInfo* bi); 282 * @param tid The thread ID to select the histories 291 ThreadID tid, Addr branch_pc, bool taken, BranchInfo* b, 301 * @param tid The Thread ID to select the histories to rollback. 310 ThreadID tid, boo [all...] |
H A D | tage_sc_l.hh | 95 ThreadID tid, Addr branch_pc, TAGEBase::BranchInfo* bi) override; 100 ThreadID tid, Addr branch_pc, bool taken, TAGEBase::BranchInfo* b, 105 int gindex(ThreadID tid, Addr pc, int bank) const override; 109 virtual uint16_t gtag(ThreadID tid, Addr pc, int bank) const override = 0; 111 void squash(ThreadID tid, bool taken, TAGEBase::BranchInfo *bi, 155 ThreadID tid, Addr branch_pc, bool cond_branch, void* &b) override; 159 void update(ThreadID tid, Addr branch_addr, bool taken, void *bp_history,
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H A D | multiperspective_perceptron.hh | 241 * @param tid Thread ID of the branch 247 virtual unsigned int getHash(ThreadID tid, Addr pc, Addr pc2, int t) 431 * @param tid Thread ID of the branch 437 unsigned int getIndex(ThreadID tid, const MPPBranchInfo &bi, 443 * @param tid Thread ID of the branch 446 void findBest(ThreadID tid, std::vector<int> &best_preds) const; 451 * @param tid Thread ID of the branch 455 int computeOutput(ThreadID tid, MPPBranchInfo &bi); 459 * @param tid Thread ID of the branch 463 void train(ThreadID tid, MPPBranchInf [all...] |
H A D | tage_sc_l_64KB.hh | 60 uint16_t gtag(ThreadID tid, Addr pc, int bank) const override; 116 int gPredictions(ThreadID tid, Addr branch_pc, BranchInfo* bi, 124 void gUpdates(ThreadID tid, Addr pc, bool taken, BranchInfo* bi,
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H A D | multiperspective_perceptron_tage_64KB.hh | 65 int gPredictions(ThreadID tid, Addr branch_pc, 70 void gUpdates(ThreadID tid, Addr pc, bool taken,
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/gem5/src/arch/mips/ |
H A D | isa.cc | 359 for (ThreadID tid = 0; tid < numThreads; tid++) { 360 TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid); 361 tcBind.curTC = tid; 362 setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid); 376 for (ThreadID tid = 1; tid < numThreads; tid++) { 377 tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid); 435 readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) argument 448 setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument 461 setRegMask(int misc_reg, RegVal val, ThreadID tid) argument 476 setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) argument [all...] |
/gem5/src/cpu/o3/ |
H A D | iew.hh | 151 void clearStates(ThreadID tid); 178 void squash(ThreadID tid); 201 void skidInsert(ThreadID tid); 233 bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } argument 242 void squashDueToBranch(const DynInstPtr &inst, ThreadID tid); 247 void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid); 250 void block(ThreadID tid); 255 void unblock(ThreadID tid); 258 void dispatch(ThreadID tid); [all...] |
H A D | fetch.hh | 247 void clearStates(ThreadID tid); 276 void drainStall(ThreadID tid); 282 void deactivateThread(ThreadID tid); 315 * @param tid Thread id. 319 bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc); 333 const DynInstPtr squashInst, ThreadID tid); 340 const InstSeqNum seq_num, ThreadID tid); 343 bool checkStall(ThreadID tid) const; 355 DynInstPtr squashInst, ThreadID tid); 365 bool checkSignalsAndUpdate(ThreadID tid); [all...] |
H A D | store_set.hh | 91 void insertStore(Addr store_PC, InstSeqNum store_seq_num, ThreadID tid); 103 void squash(InstSeqNum squashed_num, ThreadID tid);
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H A D | inst_queue.hh | 168 unsigned numFreeEntries(ThreadID tid); 174 bool isFull(ThreadID tid); 228 void commit(const InstSeqNum &inst, ThreadID tid = 0); 267 void squash(ThreadID tid); 270 unsigned getCount(ThreadID tid) { return count[tid]; }; argument 277 void doSquash(ThreadID tid);
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/gem5/src/cpu/minor/ |
H A D | cpu.cc | 169 MinorCPU::wakeup(ThreadID tid) argument 171 DPRINTF(Drain, "[tid:%d] MinorCPU wakeup\n", tid); 172 assert(tid < numThreads); 174 if (threads[tid]->status() == ThreadContext::Suspended) { 175 threads[tid]->activate(); 186 for (ThreadID tid = 0; tid < numThreads; tid++) { 187 threads[tid] [all...] |
H A D | execute.cc | 170 for (ThreadID tid = 0; tid < params.numThreads; tid++) { 171 std::string tid_str = std::to_string(tid); 183 executeInfo[tid].inFlightInsts = new Queue<QueuedInst, 187 executeInfo[tid].inFUMemInsts = new Queue<QueuedInst, 194 Execute::getInput(ThreadID tid) argument 197 if (!inputBuffer[tid].empty()) { 198 const ForwardInstData &head = inputBuffer[tid].front(); 200 return (head.isBubble() ? NULL : &(inputBuffer[tid] 207 popInput(ThreadID tid) argument 295 updateBranchData( ThreadID tid, BranchData::Reason reason, MinorDynInstPtr inst, const TheISA::PCState &target, BranchData &branch) argument 1601 ThreadID tid = interruptPriority; local [all...] |
H A D | fetch1.cc | 135 for (auto tid : priority_list) { 136 if (cpu.getContext(tid)->status() == ThreadContext::Active && 137 !fetchInfo[tid].blocked && 138 fetchInfo[tid].state == FetchRunning) { 139 threadPriority = tid; 140 return tid; 148 Fetch1::fetchLine(ThreadID tid) argument 151 Fetch1ThreadInfo &thread = fetchInfo[tid]; 161 InstId request_id(tid, 171 request->request->setContext(cpu.threads[tid] 714 wakeupFetch(ThreadID tid) argument [all...] |
H A D | pipeline.cc | 199 Pipeline::wakeupFetch(ThreadID tid) argument 201 fetch1.wakeupFetch(tid); 225 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) { 226 fetch1.wakeupFetch(tid);
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H A D | cpu.hh | 131 void wakeup(ThreadID tid) override; 145 void serializeThread(CheckpointOut &cp, ThreadID tid) const override; 146 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
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H A D | decode.hh | 132 const ForwardInstData *getInput(ThreadID tid); 135 void popInput(ThreadID tid);
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H A D | fetch2.hh | 179 const ForwardLineData *getInput(ThreadID tid); 182 void popInput(ThreadID tid); 186 void dumpAllInput(ThreadID tid);
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/gem5/src/cpu/kvm/ |
H A D | perfevent.cc | 70 PerfKvmCounter::PerfKvmCounter(PerfKvmCounterConfig &config, pid_t tid) argument 73 attach(config, tid, -1); 77 pid_t tid, const PerfKvmCounter &parent) 80 attach(config, tid, parent); 146 PerfKvmCounter::enableSignals(pid_t tid, int signal) argument 151 sigowner.pid = tid; 162 pid_t tid, int group_fd) 167 &config.attr, tid, 76 PerfKvmCounter(PerfKvmCounterConfig &config, pid_t tid, const PerfKvmCounter &parent) argument 161 attach(PerfKvmCounterConfig &config, pid_t tid, int group_fd) argument
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/gem5/src/arch/alpha/ |
H A D | isa.cc | 78 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const 98 ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid) 117 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) 143 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
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/gem5/src/cpu/simple/ |
H A D | atomic.cc | 134 for (ThreadID tid = 0; tid < numThreads; tid++) { 135 if (tid != sender) { 136 if (getCpuAddrMonitor(tid)->doMonitor(pkt)) { 137 wakeup(tid); 140 TheISA::handleLockedSnoop(threadInfo[tid]->thread, 160 for (ThreadID tid = 0; tid < numThreads; tid [all...] |