arch/mips/isa.cc

359     for (ThreadID tid = 0; tid < numThreads; tid++) {
360         TCBindReg tcBind = readMiscRegNoEffect(MISCREG_TC_BIND, tid);
361         tcBind.curTC = tid;
362         setMiscRegNoEffect(MISCREG_TC_BIND, tcBind, tid);
376     for (ThreadID tid = 1; tid < numThreads; tid++) {
377         tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
379         setMiscRegNoEffect(MISCREG_TC_STATUS, tcStatus, tid);
414 ISA::getVPENum(ThreadID tid) const
416     TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
421 ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
424         ? tid : getVPENum(tid);
435 ISA::readMiscReg(int misc_reg, ThreadContext *tc,  ThreadID tid)
438         ? tid : getVPENum(tid);
448 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
451         ? tid : getVPENum(tid);
453             "[tid:%i] Setting (direct set) CP0 Register:%u "
455             tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
461 ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid)
464         ? tid : getVPENum(tid);
466             "[tid:%i] Setting CP0 Register: %u Select: %u (%s) to %#x\n",
467             tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
476 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
479         ? tid : getVPENum(tid);
482             "[tid:%i] Setting CP0 Register:%u "
484             tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val);
543     for (ThreadID tid = 0; tid < num_threads; tid++) {
544         TCStatusReg tcStatus = readMiscRegNoEffect(MISCREG_TC_STATUS, tid);
545         TCHaltReg tcHalt = readMiscRegNoEffect(MISCREG_TC_HALT, tid);
549             haltThread(cpu->getContext(tid));
551             restoreThread(cpu->getContext(tid));