Searched refs:target (Results 51 - 75 of 114) sorted by relevance

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/gem5/src/systemc/tests/systemc/tmp/compliance_1666_2011/section_6.6/test05/
H A Dtest05.cpp53 SC_THREAD(target);
73 // ticker process killed by target
113 void target() function in struct:M3
125 cout << "sc_unwind_exception caught by target" << endl;
/gem5/src/systemc/tests/systemc/tmp/others/kill_reset/
H A Dkill_reset.cpp18 SC_THREAD(target);
38 // ticker process killed by target
77 void target() function in struct:M3
89 cout << "sc_unwind_exception caught by target" << endl;
/gem5/src/systemc/core/
H A Dsc_spawn.cc93 newReset(p.target, proc, p.sync, p.value);
96 newReset(p.target, proc, p.sync, p.value);
99 newReset(p.target, proc, p.sync, p.value);
102 newReset(i.target, proc, i.sync, i.value);
/gem5/src/cpu/pred/
H A Dindirect.hh59 const TheISA::PCState& target, ThreadID tid) = 0;
H A Dbpred_unit.hh88 * target of the branch if it is taken.
121 * @param corr_target The correct branch target.
163 * Looks up a given PC in the BTB to get the predicted target.
165 * @return The address of the target of the branch.
179 * @param corrTarget The resolved target of the branch (only needed
188 * Updates the BTB with the target of a branch.
190 * @param target_PC The branch's target that will be added to the BTB.
192 void BTBUpdate(Addr instPC, const TheISA::PCState &target) argument
193 { BTB.update(instPC, target, 0); }
211 wasCall(0), wasReturn(0), wasIndirect(0), target(MaxAdd
263 Addr target; member in struct:BPredUnit::PredictorHistory
[all...]
H A Dtage_sc_l.hh102 Addr target) override;
112 Addr target) override;
116 Addr branch_pc, Addr target);
H A Dmultiperspective_perceptron_tage.hh79 const StaticInstPtr &inst, Addr target) override;
82 bool taken, Addr branch_pc, Addr target);
124 void updateHistoryStack(Addr target, bool taken, bool is_call, argument
127 unsigned int truncated_target = target;
H A Dtage_sc_l.cc231 ThreadHistory& tHist, int brtype, bool taken, Addr branch_pc, Addr target)
238 tmp = (tmp ^ (target >> instShiftAmt));
239 path = path ^ (target >> instShiftAmt) ^ (target >> (instShiftAmt+2));
267 bool speculative, const StaticInstPtr &inst, Addr target)
281 updatePathAndGlobalHistory(tHist, brtype, taken, branch_pc, target);
290 Addr target)
230 updatePathAndGlobalHistory( ThreadHistory& tHist, int brtype, bool taken, Addr branch_pc, Addr target) argument
265 updateHistories( ThreadID tid, Addr branch_pc, bool taken, TAGEBase::BranchInfo* b, bool speculative, const StaticInstPtr &inst, Addr target) argument
289 squash(ThreadID tid, bool taken, TAGEBase::BranchInfo *bi, Addr target) argument
/gem5/site_scons/gem5_scons/
H A D__init__.py77 def __call__(self, target, source, env, for_signature=None):
86 tgts = map(strip, target)
104 # source is a substring of target, OK
107 # target is a substring of source, need to back up to
/gem5/src/systemc/tests/systemc/1666-2011-compliance/disable_enable/
H A Ddisable_enable.cpp46 SC_THREAD(target);
91 void target() function in struct:Top
/gem5/src/systemc/tests/tlm/nb2b_adapter/
H A Dnb2b_adapter.cpp208 unsigned int target = (id + offset) % init_socket.size(); // Route-through local
210 init_socket[target]->b_transport( trans, delay );
233 unsigned int target = (id + offset) % init_socket.size(); // Route-through local
236 status = init_socket[target]->nb_transport_fw( trans, phase, delay );
250 unsigned int target = (id + offset) % init_socket.size(); // Route-through local
252 bool status = init_socket[target]->get_direct_mem_ptr( trans, dmi_data );
259 unsigned int target = (id + offset) % init_socket.size(); // Route-through local
261 return init_socket[target]->transport_dbg( trans );
/gem5/src/mem/cache/prefetch/
H A Dpif.cc62 PIFPrefetcher::CompactorEntry::distanceFromTrigger(Addr target, argument
65 const Addr target_blk = target >> log_blk_size;
91 PIFPrefetcher::CompactorEntry::hasAddress(Addr target, argument
94 Addr blk_distance = distanceFromTrigger(target, log_blk_size);
96 if (target > trigger) {
98 } else if (target < trigger) {
H A Dpif.hh96 * @param target address to check
98 * @return TRUE if target has its bit set
100 bool hasAddress(Addr target, unsigned int log_blk_size) const;
/gem5/src/systemc/tests/tlm/endian_conv/
H A Dtestall.py24 transaction through a single conversion function, to a simple target
28 the same effect on initiator/target memory as a set of smaller transactions
34 target memory (as strings) and to capture their final states, so that
152 self.target = "".join(
157 r.target = self.target
160 return self.initiator==golden.initiator and self.target==golden.target
162 return self.initiator!=golden.initiator or self.target!=golden.target
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/gem5/ext/systemc/src/sysc/communication/
H A Dsc_signal.cpp51 sc_signal_invalid_writer( sc_object* target, sc_object* first_writer, argument
60 "`" << target->name() << "' "
61 "(" << target->kind() << ")"
81 check_port( sc_object* target, sc_port_base * port_, bool is_output ) argument
87 sc_signal_invalid_writer( target, m_output, port_, false );
/gem5/src/mem/cache/
H A Dnoncoherent_cache.cc252 for (auto &target: targets) {
253 Packet *tgt_pkt = target.pkt;
255 switch (target.source) {
282 completion_time - target.recvTime;
309 panic("Illegal target->source enum %d\n", target.source);
H A Dmshr.cc253 MSHR::allocate(Addr blk_addr, unsigned blk_size, PacketPtr target, argument
258 isSecure = target->isSecure();
261 assert(target);
264 _isUncacheable = target->req->isUncacheable();
273 Target::Source source = (target->cmd == MemCmd::HardPFReq) ?
275 targets.add(target, when_ready, _order, source, true, alloc_on_fill);
278 assert(target->matchBlockAddr(targets.front().pkt, blkSize));
323 * Adds a target to an MSHR
334 // have to defer the new target until after the response if any of
338 // comes back (but before this target i
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/gem5/src/arch/arm/kvm/
H A Darm_cpu.hh104 void kvmArmVCpuInit(uint32_t target);
/gem5/util/m5/
H A Dm5.c319 char *target = strtok(argv[0], sep); local
320 while (target) {
321 CPU_SET(atoi(target), &mask);
322 target = strtok(NULL, sep);
/gem5/tests/configs/
H A Dcheckpoint.py47 "target called exit()",
102 p = Process(target=_run_step,
/gem5/ext/pybind11/tests/
H A Dtest_iostream.py21 def redirect_stdout(target):
23 sys.stdout = target
32 def redirect_stderr(target):
34 sys.stderr = target
/gem5/src/systemc/tests/
H A Dverify.py66 def __init__(self, target, suffix, build_dir, props):
67 self.target = target
573 target: props for (target, props) in
582 for target, props in sorted(filtered_tests.iteritems()):
583 print('%s.%s' % (target, main_args.flavor))
589 Test(target, main_args.flavor, main_args.build_dir, props) for
590 target, props in sorted(filtered_tests.iteritems())
/gem5/ext/testlib/
H A Dhelper.py88 stdout_thread = threading.Thread(target=log_output,
91 stderr_thread = threading.Thread(target=log_output,
386 def _copy_file_keep_perms(source, target):
387 '''Copy a file keeping the original permisions of the target.'''
388 st = os.stat(target)
389 shutil.copy2(source, target)
390 os.chown(target, st[stat.ST_UID], st[stat.ST_GID])
/gem5/src/cpu/minor/
H A Dpipe_data.cc146 << ";0x" << std::hex << target.instAddr() << std::dec
155 os << branch.reason << " target: 0x"
156 << std::hex << branch.target.instAddr() << std::dec
/gem5/src/systemc/ext/core/
H A Dsc_spawn.hh137 Reset(T *t, bool v, bool s) : target(t), value(v), sync(s) {}
139 T *target; member in struct:sc_core::sc_spawn_options::Reset

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