/gem5/src/cpu/o3/ |
H A D | mem_dep_unit_impl.hh | 486 MemDepUnit<MemDepPred, Impl>::squash(const InstSeqNum &squashed_num, function in class:MemDepUnit 534 // Tell the dependency predictor to squash as well. 535 depPred.squash(squashed_num, tid);
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H A D | store_set.cc | 311 StoreSet::squash(InstSeqNum squashed_num, ThreadID tid)
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H A D | iew.hh | 178 void squash(ThreadID tid); 239 /** Sends commit proper information for a squash due to a branch 244 /** Sends commit proper information for a squash due to a memory order
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H A D | inst_queue.hh | 267 void squash(ThreadID tid); 503 /** Stat for number of non-speculative instructions removed due to a squash.
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H A D | rename.hh | 197 void squash(const InstSeqNum &squash_seq_num, ThreadID tid); 251 /** Executes actual squash, removing squashed instructions. */ 523 /** Stat for total number of mappings that were undone due to a squash. */
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H A D | rename_impl.hh | 375 DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid) function in class:DefaultRename 377 DPRINTF(Rename, "[tid:%i] [squash sn:%llu] Squashing instructions.\n", 382 // cycle and there should be space to hold everything due to the squash. 391 DPRINTF(Rename, "[tid:%i] [squash sn:%llu] " 392 "Rename will resume serializing after squash\n", 444 // Check stall and squash signals. 471 !fromCommit->commitInfo[tid].squash && 921 // If resumeUnblocking is set, we unblocked during the squash, 1335 // Check if there's a squash signal, squash i [all...] |
H A D | fetch.hh | 352 * squash should be the commit stage. 354 void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num, 588 * due to a squash. 592 * due to a squash.
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H A D | commit_impl.hh | 549 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid); 558 // If we want to include the squashing instruction in the squash, 560 // Hopefully this doesn't mess things up. Basically I want to squash 570 rob->squash(squashed_inst, tid); 576 // Send back the squash signal to tell stages that they should 577 // squash. 578 toIEW->commitInfo[tid].squash = true; 629 DPRINTF(Commit, "Squashing after squash after request, " 634 // the squash. It'll try to re-fetch an instruction executing in 647 DPRINTF(Commit, "Executing squash afte [all...] |
H A D | lsq.hh | 166 * from initiateAcc to resource deallocation at commit or squash. 169 * the LSQRequest is a TranslationState, therefore, upon squash, there must 879 squash(const InstSeqNum &squashed_num, ThreadID tid) function in class:LSQ::LSQRequest 881 thread.at(tid).squash(squashed_num);
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H A D | rob_impl.hh | 480 ROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid) function in class:ROB 483 DPRINTF(ROB, "Does not need to squash due to being empty " 490 DPRINTF(ROB, "Starting to squash within the ROB.\n");
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H A D | cpu.hh | 155 tickEvent.squash(); 301 * to squash uncommitted instructions to fully drain the pipeline. 497 /** Initiates a squash of all in-flight instructions for a given 498 * thread. The source of the squash is an external update of 517 * There's also an option to not squash delay slot instructions.*/
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H A D | inst_queue_impl.hh | 230 .desc("Number of squashed instructions iterated over during squash;" 1208 InstructionQueue<Impl>::squash(ThreadID tid) function in class:InstructionQueue 1210 DPRINTF(IQ, "[tid:%i] Starting to squash instructions in " 1219 // Also tell the memory dependence unit to squash. 1220 memDepUnit[tid].squash(squashedSeqNum[tid], tid);
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H A D | lsq_unit.hh | 252 /** Check for ordering violations in the LSQ. For a store squash if we 253 * ever find a conflicting load. For a load, only squash if we 290 void squash(const InstSeqNum &squashed_num);
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/gem5/src/cpu/pred/ |
H A D | tage_sc_l.cc | 289 TAGE_SC_L_TAGE::squash(ThreadID tid, bool taken, TAGEBase::BranchInfo *bi, function in class:TAGE_SC_L_TAGE 428 tage->squash(tid, taken, tage_bi, corrTarget);
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H A D | tournament.cc | 310 // speculatively, restored upon squash() calls, and 311 // recomputed upon update(squash = true) calls, 332 TournamentBP::squash(ThreadID tid, void *bp_history)
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H A D | simple_indirect.cc | 146 SimpleIndirectPredictor::squash(InstSeqNum seq_num, ThreadID tid)
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H A D | multiperspective_perceptron_tage.hh | 233 void squash(ThreadID tid, void *bp_history) override;
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H A D | tage_base.hh | 300 * This version of squash() is called once on a branch misprediction. 309 virtual void squash(
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H A D | multiperspective_perceptron_tage.cc | 614 tage->squash(tid, taken, bi->tageBranchInfo, corrTarget); 692 MultiperspectivePerceptronTAGE::squash(ThreadID tid, void *bp_history) function in class:MultiperspectivePerceptronTAGE
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H A D | loop_predictor.cc | 294 LoopPredictor::squash(ThreadID tid, BranchInfo *bi) function in class:LoopPredictor
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/gem5/src/arch/x86/ |
H A D | pagetable_walker.cc | 214 currState->squash(); 717 Walker::WalkerState::squash() function in class:X86ISA::Walker::WalkerState
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/gem5/src/sim/ |
H A D | eventq.hh | 388 void squash() { flags.set(Squashed); } function in class:Event
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/gem5/src/cpu/simple/ |
H A D | base.cc | 703 branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
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/gem5/src/dev/net/ |
H A D | sinic.cc | 537 intrEvent->squash(); 574 intrEvent->squash();
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H A D | ns_gige.cc | 874 intrEvent->squash(); 911 intrEvent->squash();
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